Patents by Inventor SHINICHIRO MISU

SHINICHIRO MISU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141455
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Publication number: 20170186884
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Patent number: 9634128
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Patent number: 9337189
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Patent number: 9312337
    Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Kazutoshi Nakamura
  • Publication number: 20160079369
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and a first semiconductor region provided between the first and second electrodes. A first element region includes a second semiconductor region provided between the first semiconductor region and the first electrode, a third semiconductor region provided between the first semiconductor region and the second electrode, a fourth semiconductor region provided between the third semiconductor region and the second electrode, and a third electrode provided in the first, third and fourth semiconductor regions. A second element region includes a fifth semiconductor region provided between the first semiconductor region and the first electrode, and a sixth semiconductor region provided between the first semiconductor region and the second electrode. An isolation region includes a seventh semiconductor region provided between the first semiconductor region and the second electrode.
    Type: Application
    Filed: September 2, 2015
    Publication date: March 17, 2016
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai
  • Patent number: 9257507
    Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Kazutoshi Nakamura
  • Publication number: 20150311326
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Patent number: 9159722
    Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Ryohei Gejo, Norio Yasuhara
  • Publication number: 20150263149
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, an insulating region, and a third semiconductor region. The first semiconductor region is of a first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and contacts the first electrode. The second semiconductor region is of a second conductivity type. The second conductor region is provided between the first semiconductor region and the second electrode. The insulating region extends from the second electrode to a side of the first semiconductor region. The third semiconductor region is of the first conductivity type. The third semiconductor region is provided in at least a portion of a region between the second semiconductor region and the insulating region, and contacts the first semiconductor region.
    Type: Application
    Filed: September 12, 2014
    Publication date: September 17, 2015
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Publication number: 20150263144
    Abstract: According to one embodiment, an insulated gate bipolar transistor includes a main region, a sense region, and a semiconductor layer that is provided between the main region and the sense region, is in contact with a collector layer of a first conductivity type provided in the main region and the sense region, and has one of a dopant concentration lower than a dopant concentration of the collector layer or a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Shinichiro MISU, Tsuneo OGURA
  • Publication number: 20150243656
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Patent number: 9059236
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Publication number: 20150155277
    Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.
    Type: Application
    Filed: July 24, 2014
    Publication date: June 4, 2015
    Inventors: Tsuneo OGURA, Shinichiro MISU, Ryohei GEJO, Norio YASUHARA
  • Publication number: 20150069461
    Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro MISU, Kazutoshi NAKAMURA
  • Publication number: 20140124832
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 8, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Publication number: 20140077261
    Abstract: An upper part of the termination region of the semiconductor substrate, an upper surface of the first diffusion layers and an upper surface of the first oxide film is etched in such a manner that the level of the upper surface of the semiconductor substrate in the termination region including the first oxide film and the first diffusion layers is lower than the level of the upper surface of the semiconductor substrate in the cell region. Then, a second oxide film is formed on the semiconductor substrate. An electrode is formed on the second oxide film so as to extend from the first region toward the cell region to the first diffusion layers in such a manner that the level of an upper surface of the electrode is lower than the level of the upper surface of the semiconductor substrate in the cell region.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi Oshino, Tomoko Matsudai, Kazutoshi Nakamura, Shinichiro Misu, Takuma Hara
  • Publication number: 20130248998
    Abstract: According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Tsuyoshi Ota, Tatsuya Nishiwaki, Takeshi Uchihara, Yusuke Kawaguchi
  • Publication number: 20130069151
    Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first conductive portion extending in a first direction perpendicular to a major surface of the substrate; a second conductive portion extending in the first direction; a semiconductor portion provided between the first and the second conductive portions and including a first semiconductor region; a first electrode portion extending in the first direction between the first and the second conductive portions; a second electrode portion extending in the first direction between the first and the second conductive portions; a first insulting portion provided between the first electrode portion and the semiconductor portion and having a first thickness; and a second insulating portion provided between the second electrode portion and the semiconductor portion and having a second thickness greater than the first thickness.
    Type: Application
    Filed: March 19, 2012
    Publication date: March 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: TSUYOSHI OHTA, SHINICHIRO MISU, MASATOSHI ARAI