Abstract: According to the signal processing apparatus of the present invention, in a text signal processing circuit, predetermined signal processes are executed to a luminance signal Y and color difference signals U and V in which a ratio of sampling clocks is equal to (4:4:4) and resultant signals are supplied to a mixing circuit. In a video signal processing circuit, predetermined signal processes are executed to the signals Y, U, and V in which a ratio of sampling clocks is equal to (4:1:1) or (4:2:2). The signal Y is supplied to the mixing circuit through a delay adjusting circuit and the high frequency components are removed from the signals U and V by a band limiting filter and, after that, the resultant signals are supplied to the mixing circuit. The signal mixed by the mixing circuit is supplied to a LPF through a D/A converter. In the LPF, the signal is demodulated by the band limiting filter according to (4:4:4).

Abstract: The invention provides an image processing apparatus and method as well as a providing medium by which deterioration of the vertical resolution is prevented and conspicuous appearance of line flickering is suppressed. In order to convert an interlaced video signal having 525 scanning lines into another progressive video signal having 525 scanning lines while maintaining the image size, in an odd-numbered field, a line after conversion is offset by 0.5 H (H is the distance between horizontal scanning lines of the inputted video signal). Consequently, pixel data of each line Oi are produced from pixel data of two lines Ii and Ii+1 before conversion. As a result, pixels of a line on the boundary between white pixels and black pixels have a gray color. In an odd-numbered field, no offset is given, and pixel data of each line I1 of the field before conversion are set as they are as pixel data of each line Oi of the field after conversion.

Abstract: The invention provides an image processing apparatus and method as well as a providing medium by which deterioration of the vertical resolution is prevented and conspicuous appearance of line flickering is suppressed. In order to convert an interlaced video signal having 525 scanning lines into another progressive video signal having 525 scanning lines while maintaining the image size, in an odd-numbered field, a line after conversion is offset by 0.5 H (H is the distance between horizontal scanning lines of the inputted video signal). Consequently, pixel data of each line Oi are produced from pixel data of two lines Ii and Ii+1 before conversion. As a result, pixels of a line on the boundary between white pixels and black pixels have a gray color. In an odd-numbered field, no offset is given, and pixel data of each line I1 of the field before conversion are set as they are as pixel data of each line Oi of the field after conversion.

Abstract: The present invention is to suppress against image deterioration in data broadcast thereby providing display with quality. A video signal separated from a reception signal by a demultiplexer is outputted to a converter section through an MPEG decoder section. A CPU, when the video signal is a data broadcast and in a 480I signal format, controls a converter section to perform size-scaling on the video signal and convert it into a 480p signal format. A data processing section generates a video signal having a 480p signal format of a corresponding character or figure, under control of the CPU, on the basis of a data signal. A synthesizer section synthesizes together the two video signals processed by the converter section and data processing section and input the synthesized signal to a D/A converter. The D/A converter converts a input video signal into an analog signal and outputs it to a display unit.

Abstract: There is provided delay means for allowing a delay difference to be provided between the timing of image size information which is set into writing side memory control means and the timing of image size information which is set into reading side memory control means in a manner such that the image size when data is written into first and second field memories and the image size when the data is read out from the first and the second field memories coincide. The image size information is set into the writing side memory control means and the reading side memory control means so as to have a delay difference between them. The image size is set by controlling the first and the second field memories in accordance with the image size information by the writing side memory control means and the reading side memory control means.

Abstract: According to the signal processing apparatus of the present invention, in a text signal processing circuit, predetermined signal processes are executed to a luminance signal Y and color difference signals U and V in which a ratio of sampling clocks is equal to (4:4:4) and resultant signals are supplied to a mixing circuit. In a video signal processing circuit, predetermined signal processes are executed to the signals Y, U, and V in which a ratio of sampling clocks is equal to (4:1:1) or (4:2:2). The signal Y is supplied to the mixing circuit through a delay adjusting circuit and the high frequency components are removed from the signals U and V by a band limiting filter and, after that, the resultant signals are supplied to the mixing circuit. The signal mixed by the mixing circuit is supplied to a LPF through a D/A converter. In the LPF, the signal is demodulated by the band limiting filter according to (4:4:4).

Abstract: Viewing of a program at optimum image quality is realized. A correspondence table of combinations of MPEG video encoding parameters and image signal processing parameters is stored in a RAM. A CPU reads out from the RAM an image signal processing parameter corresponding to a combination of MPEG video encoding parameters supplied from a demultiplexer, and on the basis of the image signal processing parameter, controls image signal processing in an image signal processor.

Abstract: An information-processing device receives and processes predetermined program data. The information-processing device includes an extracting unit for extracting image data and audio data of a program selected by a user, an obtaining unit for obtaining information related to the selected program, and a setting unit for setting a control parameter for controlling an image data display or an audio data output of the selected program in accordance with the related information.

Abstract: Viewing of a program is enabled at optimum image quality. A correspondence table of an image signal processing parameter and a combination of TMCC information and transmission errors is stored in a RAM. A CPU reads out an image signal processing parameter corresponding to a combination of TMCC information supplied from an IF demodulator and transmission errors supplied from the IF demodulator, a demultiplexer and an MPEG video decoder from the correspondence table stored in the RAM, and controls signal processing in an image signal processing portion and display processing in an image display portion based on the image signal processing parameter.

Abstract: A picture processing apparatus for picture-in-picture applications where the number of pixels n in the horizontal direction of an original picture, the number of pixels m in the vertical direction thereof, the number of pixels N in the horizontal direction of the converted picture, and the number of pixels M in the vertical direction thereof are supplied to a dividing device. Thus, ratios A=N/n and B=M/m are obtained. The inverse number 1/A of the value A is cumulated by circuits. An address generating circuit generates addresses at four points for calculating a density value a of a converted pixel corresponding to the integer part of a cumulated value &Sgr;(1/A). These addresses are supplied to memories. The pixel data at the four points that are read from the memories are supplied to respective multiplying devices. The decimal part of the value &Sgr;(1/A) is supplied as an interpolating coefficient p to a multiplying device. A coefficient (1−q) is supplied to a multiplying device.

Abstract: In a divider, a ratio of a magnification or a reduction of an image is set from a writing range and a reading range. In a horizontal interpolating circuit and a vertical interpolating circuit, an interpolation is performed on the basis of the magnification ratio. In the horizontal interpolating circuit and the vertical interpolating circuit, an interpolation is performed on the basis of the reduction ratio. In a field memory, a portion of the image of an arbitrary size at an arbitrary position is written on the basis of a control signal which is supplied from a write memory control circuit. The image is read out from the memory on the basis of a control signal which is supplied from a read memory control circuit.

Abstract: An input image signal is converted into a digital form in an A/D converter 6 by clock pulses 53 from VCO 4 of a PLL circuit 1. The frequency of the clock pulses 53 is fixed. After the number of scanning lines is converted in a primary processing circuit 7, the digital image signal is written in field memory 10. The image signal is read out from the field memory 10 by second clock pulses 63 generated in a PLL circuit 11. A frequency divider 15 in the PLL circuit 11 is changed in frequency division ratio by a control signal. As a result, the sampling number in one horizontal period of the image signal read out from the field memory 10 is changed. Since the number of pixels in the effective image period of the image signal written in the memory is constant, by changing the sampling number in one horizontal period on the read-out side, the ratio of the effective image period relative to one horizontal period can be changed to adjust the horizontal size.

Abstract: An interpolation interval Vdp obtained by the picture sizes of the original picture and the converted picture is cumulated by an adder. In the odd field, a selector selects [0.5] as an offset corresponding to an odd/even field determination signal. In the even field, the selector selects [0] as an offset corresponding to the odd/even field determination signal. In a vertical blanking interval, the offset is selected as an output. Thus, in the odd field, the offset value [0.5] is added to the cumulated value of Vdp. Thereafter, Vdp is cumulated again. Corresponding to the cumulated value, a line read address n and linear interpolating coefficients qn1 and qn2 are obtained. When Vdp is cumulated, offsets corresponding to the scanning start points in the odd field and the even field are added. Thus, the interlace accuracy is kept.

Abstract: When an image size is changed by using a linear interpolating process, a picture quality is improved so as not to overlap the position of an original signal and the position of an interpolation signal. An interpolation interval Vdp which is derived from an original image and an image size after the conversion is stored into a register of an input side and is accumulated and added by an adder from a register of an output side through a selector. A predetermined calculation is performed and an offset value q.sub.0 is obtained in a circuit. The value q.sub.0 is selected by the selector and the register of the output side is initialized for a vertical blanking period. Thus, a value (.delta.+nVdp) in which the value q.sub.0 was added to the accumulation value of Vdp is derived. On the basis of the value (.delta.+nVdp), a read address (n) of the original image and linear interpolation coefficients q.sub.n1 and q.sub.n2 are obtained.

Abstract: A picture processing apparatus and method for enlarging and reducing a picture wherein when a picture is reduced, horizontally adjacent pixel data is supplied from a delaying device to a horizontally interpolating circuit. With the pixel data, a coefficient p and a 1's complement (1-p) thereof supplied from an interpolation coefficient circuit, an interpolating process in the horizontal direction is performed. In addition, a pixel at the position of p=1 is thinned out. Pixel data that has been interpolated in the horizontal and vertical directions and that has been thinned out is written to a memory. When a picture is enlarged, pixel data that is read from a memory is delayed by two line memories and two adjacent pixels are properly selected by a switch circuit. A vertically interpolating circuit performs an interpolating process in the vertical direction. When pixel data is read from the memory, particular pixel data is read twice depending on a magnification.