Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Abstract: A memory system includes a nonvolatile semiconductor memory and a memory controller circuit. The memory controller circuit selects first and second blocks of the nonvolatile semiconductor memory, the first block being a garbage collection target block, the second block being a wear leveling target block or a refresh target block, relocates first data which is valid data stored in the first block in a series of write operations to a third block including first and second write operations, the third block being a block of the nonvolatile semiconductor memory having a free region, and relocates second data which is valid data stored in the second block in a series of write operations to a fourth block including a third write operation, the fourth block having a free region and being different from the third block, wherein the third write operation is performed between the first and second write operations.

Abstract: A memory system includes a nonvolatile semiconductor memory and a memory controller circuit. The memory controller circuit selects first and second blocks of the nonvolatile semiconductor memory, the first block being a garbage collection target block, the second block being a wear leveling target block or a refresh target block, relocates first data which is valid data stored in the first block in a series of write operations to a third block including first and second write operations, the third block being a block of the nonvolatile semiconductor memory having a free region, and relocates second data which is valid data stored in the second block in a series of write operations to a fourth block including a third write operation, the fourth block having a free region and being different from the third block, wherein the third write operation is performed between the first and second write operations.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller circuitry. The nonvolatile memory includes a first block and a second block. Each of the first block and the second block includes a plurality of first unit areas. The controller circuitry sets each of a first number of first unit areas among the plurality of first unit areas included in the first block as a second unit area. The controller circuitry sets each of a second number of first unit areas among the plurality of first unit areas included in the second block as the second unit area. The controller circuitry correlates the second unit areas included in the first block and the second block with a plurality of logical addresses in a one-to-one correspondence manner.

Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.

Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.

Abstract: A storage device includes a volatile memory, an auxiliary power source, a nonvolatile memory, a write module, and an inhibition module. The volatile memory stores user data. The auxiliary power source supplies power to the volatile memory when power from a main power source is cut off. The nonvolatile memory is written with the user data, write incomplete information indicating the user data, and power off information indicating that power from the main power source is cut off. While supplied with power from the auxiliary power source when power from the main power source is cut off, the write module writes the write incomplete information, the user data, and the power off information to the nonvolatile memory. The inhibition module inhibits reading of the user data if the power off information is not written in the nonvolatile memory when the volatile memory is supplied with power.

Abstract: According to one embodiment, a storage device includes a volatile memory, an auxiliary power source, a nonvolatile memory, a write module, and an inhibition module. The volatile memory stores user data. The auxiliary power source supplies power to the volatile memory when power from a main power source is cut off. The nonvolatile memory is written with the user data, write incomplete information indicating the user data, and power off information indicating that power from the main power source is cut off. While supplied with power from the auxiliary power source when power from the main power source is cut off, the write module writes the write incomplete information, the user data, and the power off information to the nonvolatile memory. The inhibition module inhibits reading of the user data if the power off information is not written in the nonvolatile memory when the volatile memory is supplied with power.

Abstract: According to one embodiment, an arbiter transmits its own arbitration signal from a port to a fibre channel loop in order to acquire a possessory right for the fibre channel loop when a data transmission request has occurred at the port. A detector detects a latency time from when its own arbitration signal is transmitted until the possessory right is acquired. A frame transmitter transmits a frame with a burst length corresponding to the detected latency time from the port to a destination via the fibre channel loop.

Abstract: According to one embodiment, a storage device includes a physical address specifying module, a logical address group specifying module, a data writer, and a storage controller. The physical address specifying module specifies a physical address of write destination of data received together with a logical address among physical addresses each representing a block group including a block of each of flash memories connected in parallel the storage area of which is divided into a plurality of blocks for each sector. The logical address group specifying module specifies a logical address group including logical addresses based on the logical address. The data writer writes data of the logical addresses to blocks in the physical address. The storage controller stores the physical address where the data is written and the logical address group from which the data is written in an address conversion map in association with each other.