Patents by Inventor Shinichiro Ohshige

Shinichiro Ohshige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7216325
    Abstract: A routing method of a semiconductor device includes steps (a) to (c). The step (a) checks a relation between a first interconnection pattern to be routed and a second interconnection pattern to be routed, wherein a line width of the second interconnection pattern is thicker than that of the first interconnection pattern. The step (b) refers to a routing rule of a design rule corresponding to a connection between the first interconnection pattern and the second interconnection pattern, when the first interconnection pattern and the second interconnection pattern would be routed in a same layer and connected each other. The step (c) routes the first interconnection pattern and the second interconnection such that the first interconnection is not bent in an area defined based on the routing rule.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: May 8, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Shinichiro Ohshige
  • Publication number: 20060151810
    Abstract: A semiconductor device has: a plurality of first power supply wires formed in a first wiring layer; a plurality of second power supply wires formed in a second wiring layer; and a plurality of vias connecting between the first wiring layer and the second wiring layer. The plurality of second power supply wires overlap the plurality of first power supply wires at a plurality of intersections. The plurality of vias are arranged regularly at a part of the plurality of intersections.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 13, 2006
    Inventor: Shinichiro Ohshige
  • Publication number: 20050081176
    Abstract: A routing method of a semiconductor device includes steps (a) to (c). The step (a) checks a relation between a first interconnection pattern to be routed and a second interconnection pattern to be routed, wherein a line width of the second interconnection pattern is thicker than that of the first interconnection pattern. The step (b) refers to a routing rule of a design rule corresponding to a connection between the first interconnection pattern and the second interconnection pattern, when the first interconnection pattern and the second interconnection pattern would be routed in a same layer and connected each other. The step (c) routes the first interconnection pattern and the second interconnection such that the first interconnection is not bent in an area defined based on the routing rule.
    Type: Application
    Filed: October 8, 2004
    Publication date: April 14, 2005
    Inventor: Shinichiro Ohshige