Patents by Inventor Shinichiro Takasu

Shinichiro Takasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5808745
    Abstract: A silicon wafer measuring method includes: (a) a first step of measuring a light transmission characteristic (I.sub.OBS) of the pulled silicon wafer by utilizing parallel polarized light incident at the Brewster angle into the pulled silicon wafer, (b) a second step of measuring a light transmission characteristic (I.sub.O) of a floating zone silicon wafer functioning as a reference silicon wafer by utilizing parallel polarized light incident at the Brewster angle into the floating zone silicon wafer, and (c) a third step of calculating a substitutional carbon concentration ?C.sub.SC ! on the basis of the light transmission characteristic (I.sub.OBS) of the pulled silicon wafer measured during the first step and the light transmission characteristic (I.sub.O) of the floating zone silicon wafer measured during the second step, (d) a fourth step of comparing the substitutional carbon concentration ?C.sub.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: September 15, 1998
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hiroshi Shirai, Mikio Watanabe, Shinichiro Takasu
  • Patent number: 5287167
    Abstract: The invention related to a method for determining a silicon wafer in which the interstitial oxygen concentration of a pulled silicon wafer is calculated on the basis of a light transmission characteristic measured by utilizing parallel polarized light incident at the brewster angle into the pulled silicon wafer and a further light transmission characteristic measured by utilizing parallel polarized light incident at the brewster angle into the floating zone silicon wafer function as a reference silicon wafer. The interstitial oxygen concentration value of the pulled silicon wafer is compared with a reference value to determine a defect in pulled silicon wafer.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: February 15, 1994
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hiroshi Shirai, Mikio Watanabe, Shinichiro Takasu
  • Patent number: 4479297
    Abstract: A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO.sub.2 and Si is proposed.This method is characterized in that a single crystalline CeO.sub.2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO.sub.2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO.sub.2 insulation layer and reacting the oxygen ions with the single crystalline Si.An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO.sub.2 insulation layer.Predetermined processes, such as forming a single crystalline CeO.sub.2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.
    Type: Grant
    Filed: June 9, 1982
    Date of Patent: October 30, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yoshihisa Mizutani, Shinichiro Takasu
  • Patent number: 4411013
    Abstract: An X-ray system for transferring a fine pattern onto a target has a mask, on the surface of which is formed an X-ray absorbing layer in a predetermined pattern and which is made of a single crystal of high regularity. Parallel monochromic X-rays become incident on the lattice plane of the single crystal at an angle .theta.. Diffraction X-rays emerging from the lattice plane are projected onto the surface of a wafer in the normal direction. An X-ray resist layer is formed on the surface of the wafer. Since incident X-rays and diffraction X-rays are absorbed by the X-ray absorbing layer on the mask, the pattern defined by the layer is projected on the X-ray resist layer.
    Type: Grant
    Filed: December 18, 1981
    Date of Patent: October 18, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shinichiro Takasu, Toshiaki Shinozaki
  • Patent number: 4378269
    Abstract: A method of manufacturing a single crystal silicon rod by the pulling method which is characterized in that the intracrystal temperature of the growing single crystal silicon rod is reduced from 900.degree. to 500.degree. C. in less than 4 hours.
    Type: Grant
    Filed: June 24, 1981
    Date of Patent: March 29, 1983
    Assignee: VLSI Technology Research Association
    Inventors: Yoshiaki Matsushita, Shinichiro Takasu, Seigo Kishino
  • Patent number: 4291990
    Abstract: An optical apparatus for measuring irregularities on the mirror surface of, for example, a silicon wafer used to provide a semiconductor integrated circuit. Irradiates on the mirror surface light fluxes arranged in a special form, for example, in the lattice form. By observing the pattern of light fluxes reflected from said mirror surface, one can measure the surface irregularities. A light flux issued from a light source is divided by a photomask or diffraction grating into first light fluxes irradiated all over the mirror surface and second light fluxes surrounding the respective first light fluxes in the continuous or discontinuous annular form, thereby ensuring the simultaneous measurement of the distribution of extensive irregularities over the entire mirror surface by the first light fluxes and the distribution of local irregularities on said mirror surface by the second light fluxes.
    Type: Grant
    Filed: January 22, 1979
    Date of Patent: September 29, 1981
    Assignee: VLSI Technology Research Association
    Inventor: Shinichiro Takasu