Patents by Inventor Shinichiro Takatani
Shinichiro Takatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9064704Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.Type: GrantFiled: February 15, 2013Date of Patent: June 23, 2015Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chih-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Patent number: 8970998Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: GrantFiled: December 31, 2012Date of Patent: March 3, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Patent number: 8969973Abstract: A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the OFF-state linearity while retaining a low insertion loss, and minimizing the area occupied by the resistor and hence the total chip size.Type: GrantFiled: July 2, 2010Date of Patent: March 3, 2015Assignee: Win Semiconductors Corp.Inventor: Shinichiro Takatani
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Patent number: 8964342Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resistor, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: GrantFiled: December 31, 2012Date of Patent: February 24, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Publication number: 20140312390Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.Type: ApplicationFiled: June 7, 2013Publication date: October 23, 2014Inventors: Shu-Hsiao TSAI, Hsiu-Chen CHANG, Shinichiro TAKATANI, Cheng-Kuo LIN
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Publication number: 20140231876Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Applicant: WIN Semiconductors Corp.Inventors: Shu-Hsiao TSAI, Cheng-Kuo LIN, Bing-Shan HONG, Shinichiro Takatani
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Publication number: 20140231875Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chih-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140209926Abstract: A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
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Publication number: 20140183544Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140183609Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resister, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140097515Abstract: A compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A SiN protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.Type: ApplicationFiled: December 12, 2013Publication date: April 10, 2014Applicant: WIN Semiconductors Corp.Inventor: Shinichiro TAKATANI
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Patent number: 8676132Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.Type: GrantFiled: November 15, 2012Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Shigeki Koya, Shinichiro Takatani, Takashi Ogawa, Akishige Nakajima, Yasushi Shigeno
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Publication number: 20140054608Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Yu-Kai WU
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Publication number: 20130320402Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure and the fabrication method thereof, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT's structure comprises a buffer layer, a barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. The fabrication method of an HBT and a pHEMT are also included.Type: ApplicationFiled: October 26, 2012Publication date: December 5, 2013Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shu-Hsiao TSAI, Cheng-Kuo LIN, Bing-Shan HONG, Shinichiro TAKATANI
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Publication number: 20130140671Abstract: The present invention relates to a compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: WIN Semiconductors Corp.Inventor: Shinichiro TAKATANI
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Publication number: 20130069708Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.Type: ApplicationFiled: November 15, 2012Publication date: March 21, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shigeki Koya, Shinichiro Takatani, Takashi Ogawa, Akishige Nakajima, Yasushi Shigeno
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Patent number: 8385847Abstract: A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.Type: GrantFiled: February 25, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Ogawa, Shinichiro Takatani, Shigeki Koya, Hiroyuki Takazawa, Shinya Osakabe, Akishige Nakajima, Yasushi Shigeno
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Patent number: 8335479Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.Type: GrantFiled: April 16, 2012Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Shigeki Koya, Shinichiro Takatani, Takashi Ogawa, Akishige Nakajima, Yasushi Shigeno
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Patent number: 8330524Abstract: A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.Type: GrantFiled: March 13, 2012Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
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Publication number: 20120229192Abstract: A semiconductor integrated circuit which reduces an increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.Type: ApplicationFiled: March 13, 2012Publication date: September 13, 2012Inventors: Kaoru KATOH, Shigeki KOYA, Shinichiro TAKATANI, Yasushi SHIGENO, Akishige NAKAJIMA, Takashi OGAWA