Patents by Inventor Shinichiro Wada

Shinichiro Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090160016
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 25, 2009
    Inventors: Mitsuru ARAI, Shinichiro Wada, Hideaki Nonami
  • Publication number: 20090014838
    Abstract: The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor are formed on each epitaxial collector layer having the same thickness and are provided with a buried collector region formed in the same process and having the same impurity profile, the buried collector region exists immediately under a base of the high-speed bipolar transistor, no buried collector region and no SIC region exist immediately under a base of the high voltage bipolar transistor and distance between a base region and a collector plug region of the high voltage bipolar transistor is equal to or is longer than the similar distance of the high-speed bipolar transistor.
    Type: Application
    Filed: June 23, 2008
    Publication date: January 15, 2009
    Inventors: Mitsuru ARAI, Shinichiro Wada, Hideyuki Hosoe
  • Publication number: 20080036036
    Abstract: To easily obtain a resistance element with an adjustable resistance value, wherein the resistance value is within 1% or less of a desired design value, having a low parasitic capacitance and which permits a relatively large current to flow, in a semiconductor device wherein resistance elements are incorporated in a semiconductor substrate, the resistance values of the resistance elements can be adjusted within a fixed range, the first resistance element and second resistance element are disposed adjacent to each other within 500 ?m, and both terminals of the second resistance element have two pads which are drawn out therefrom.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 14, 2008
    Inventor: Shinichiro Wada
  • Publication number: 20060175635
    Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.
    Type: Application
    Filed: January 19, 2006
    Publication date: August 10, 2006
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Patent number: 6998881
    Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 14, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Wada, Satoshi Ueno, Shinya Kajiyama
  • Patent number: 6924544
    Abstract: A semiconductor device with a resistor element whose the resistance value can be adjusted to a desired value without changing dimensions thereof is provided. The resistor element is formed of a poly-Si layer formed on an insulator over a semiconductor substrate. An impurity is introduced into the poly-Si layer by the use of ion implantation. In the vicinity of both ends of the poly-Si layer forming the resistor element, silicide layers each made of cobalt silicide or the like are formed over an upper surface of the poly-Si layer. The area of one silicide layer is larger than that of the other silicide layer. By adjusting the area of the one silicide layer, the length between the silicide layers is adjusted and the resistance value of the resistor element can be adjusted without changing the shape of the poly-Si layer.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 2, 2005
    Assignees: Hitachi, Ltd., Hitachi Display Devices, Ltd.
    Inventors: Shinichiro Wada, Hiromi Shimamoto
  • Publication number: 20050040869
    Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
    Type: Application
    Filed: September 24, 2004
    Publication date: February 24, 2005
    Inventors: Shinichiro Wada, Satoshi Ueno, Shinya Kajiyama
  • Patent number: 6809562
    Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: October 26, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Wada, Satoshi Ueno, Shinya Kajiyama
  • Publication number: 20040183157
    Abstract: A semiconductor device with a resistor element whose the resistance value can be adjusted to a desired value without changing dimensions thereof is provided. The resistor element is formed of a poly-Si layer formed on an insulator over a semiconductor substrate. An impurity is introduced into the poly-Si layer by the use of ion implantation. In the vicinity of both ends of the poly-Si layer forming the resistor element, silicide layers each made of cobalt silicide or the like are formed over an upper surface of the poly-Si layer. The area of one silicide layer is larger than that of the other silicide layer. By adjusting the area of the one silicide layer, the length between the silicide layers is adjusted and the resistance value of the resistor element can be adjusted without changing the shape of the poly-Si layer.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Applicants: Hitachi, Ltd., Hitachi Display Devices, Ltd.
    Inventors: Shinichiro Wada, Hiromi Shimamoto
  • Publication number: 20030222686
    Abstract: In a circuit for converting an input signal Datal of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.
    Type: Application
    Filed: April 11, 2003
    Publication date: December 4, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinichiro Wada, Satoshi Ueno, Shinya Kajiyama
  • Patent number: 6122412
    Abstract: An image reading unit reads an original image, one main scan line by one main scan line, in a sub-scan direction. A window setting unit sets a measuring window in a bit-map formation of image data obtained through the image reading unit, in a manner in which the measuring window moves in a predetermined manner so that the measuring window appropriately includes pixels of an oblique line image which is formed in the bit-map formation of image data as a result of being read through the image reading unit. A position error measuring unit processes image data defined by the measuring window, and, thus, measures an error of the oblique line image formed in the bit-map formation of obtained image data between a predetermined reference state and an actual reading state.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: September 19, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Noguchi, Hideyuki Takemoto, Shinichiro Wada
  • Patent number: 6078703
    Abstract: An image reading unit reads an original image, one main scan line by one main scan line, in a sub-scan direction. A window setting unit sets a measuring window in a bit-map formation of image data obtained through the image reading unit, in a manner in which the measuring window moves in a predetermined manner so that the measuring window appropriately includes pixels of an oblique line image which is formed in the bit-map formation of image data as a result of being read through the image reading unit. A position error measuring unit processes image data defined by the measuring window, and, thus, measures an error of the oblique line image formed in the bit-map formation of obtained image data between a predetermined reference state and an actual reading state.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: June 20, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Noguchi, Hideyuki Takemoto, Shinichiro Wada
  • Patent number: 6023538
    Abstract: An image reading unit reads an original image, one main scan line by one main scan line, in a sub-scan direction. A window setting unit sets a measuring window in a bit-map formation of image data obtained through the image reading unit, in a manner in which the measuring window moves in a predetermined manner so that the measuring window appropriately includes pixels of an oblique line image which is formed in the bit-map formation of image data as a result of being read through the image reading unit. A position error measuring unit processes image data defined by the measuring window, and, thus, measures an error of the oblique line image formed in the bit-map formation of obtained image data between a predetermined reference state and an actual reading state.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: February 8, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Noguchi, Hideyuki Takemoto, Shinichiro Wada
  • Patent number: 6023537
    Abstract: An oblique line pattern is located outside of an effective image area and comprises a plurality of lines with a fixed inclination to the main scan direction. A reading unit, extending in the main scan direction, reads the oblique line pattern together with an original image which is placed in the effective image area. A setting portion is provided for an operator to set an image size change rate for the original image. A sub-scanning portion changes an original image scanning speed in a sub-scan direction according to the image size change rate. A first calculating portion sets a window on image data of the oblique line pattern obtained through the reading unit, and calculates a center of gravity of the image data in the window. A controlling portion controls movement of the window according to a value of the center of gravity obtained through the first calculating portion.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: February 8, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinichiro Wada, Koichi Noguchi
  • Patent number: 5949924
    Abstract: An image reading unit reads an original image, one main scan line by one main scan line, in a sub-scan direction. A window setting unit sets a measuring window in a bit-map formation of image data obtained through the image reading unit, in a manner in which the measuring window moves in a predetermined manner so that the measuring window appropriately includes pixels of an oblique line image which is formed in the bit-map formation of image data as a result of being read through the image reading unit. A position error measuring unit processes image data defined by the measuring window, and, thus, measures an error of the oblique line image formed in the bit-map formation of obtained image data between a predetermined reference state and an actual reading state.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: September 7, 1999
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Noguchi, Hideyuki Takemoto, Shinichiro Wada
  • Patent number: 5949922
    Abstract: First and second patterns are located outside of an image reading area. A first pattern comprises a plurality of lines each extending at a fixed angle with respect to a sub-scan direction. A second pattern comprises a plurality of lines each extending at a fixed angle but having a reverse direction with respect to the sub-scan direction. An image reading portion reads the first and second patterns. A position error measuring portion measures first and second image reading position errors corresponding to different angle oblique lines of the first and second patterns of image data obtained as a result of reading the first and second patterns, respectively. The position error measuring portion compensates for position deviations of the first and second patterns using the first and second image reading position errors, and obtains position-deviation-compensated image reading position errors.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: September 7, 1999
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinichiro Wada, Koichi Noguchi, Masayoshi Watanuki
  • Patent number: 5892595
    Abstract: An image reading apparatus includes a reference pattern having slanting lines, which is provided outside a reading range and read by image sensors arranged at separate positions in a sub-scanning direction. A reference-position determining unit detects one of the slanting lines in the reference pattern based on image data output from one of the image sensors so that a position of the image data when one of the slanting lines is detected is determined as a reference position. First and second delay units have line memories which store image data read out from an original image having lines, the delay units delaying outputting of the image data from the line memories line by line. First and second determining units determine image data having color values at imaginary points. An error measurement unit selects one of the imaginary points whose image data has a minimum difference between the color values of the image data.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: April 6, 1999
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinji Yamakawa, Koichi Noguchi, Shinichiro Wada
  • Patent number: 5565907
    Abstract: An image forming apparatus capable of producing a high quality halftone image stably and rendering faithful tonality. For a bilevel image, the apparatus smooths the boundary between black and white. For a multilevel image, the apparatus obviates solitary dots for thereby causing dots to concentrate. As a result, a bilevel image and a multilevel image are provided with a clear boundary.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: October 15, 1996
    Assignee: Ricoh Company, Ltd.
    Inventors: Shinichiro Wada, Takahiro Yagishita
  • Patent number: 5194879
    Abstract: An image forming apparatus includes a laser beam scanning unit for scanning a recording medium in synchronism with a writing clock signal so that a dotted image is formed on the recording medium, a counter for carrying out a count operation in synchronism with the writing clock signal so that one count value or a plurality of count values determining a scanning area is/are obtained, a first controller for activating or inactivating the laser beam scanning unit based on one or the plurality of count values, a dip switch unit for specifying a dotting density, a second controller for controlling the frequency of the writing clock signal and/or a speed of scanning; and a changing unit for changing one or the plurality of count values, which should be obtained by the counter, based on the dotting density specified by the dip switch unit, so that the position of the scanning area with respect to the recording medium is constant even if the frequency of the writing clock signal and/or the scanning speed are changed
    Type: Grant
    Filed: February 21, 1991
    Date of Patent: March 16, 1993
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroaki Kotabe, Shigeru Yamazaki, Kouji Yamanobe, Masaru Kaneko, Yasushi Nakazato, Masahiko Banno, Shinichiro Wada, Akihiko Motegi, Kazuya Iwasaki, Takashi Nishizawa