Patents by Inventor Shinichiro Yamaguchi
Shinichiro Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107157Abstract: The present disclosure relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device capable of improving auto-focusing accuracy by using a phase difference signal obtained by using a photoelectric conversion film. The solid-state imaging device includes a pixel including a photoelectric conversion portion having a structure where a photoelectric conversion film is interposed by an upper electrode on the photoelectric conversion film and a lower electrode under the photoelectric conversion film. The upper electrode is divided into a first upper electrode and a second upper electrode. The present disclosure can be applied to, for example, a solid-state imaging device or the like.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keisuke HATANO, Fumihiko KOGA, Tetsuji YAMAGUCHI, Shinichiro IZAWA
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Patent number: 6453391Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other.Type: GrantFiled: June 18, 2001Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Publication number: 20010032301Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect a same operation in synchronism with each other.Type: ApplicationFiled: June 18, 2001Publication date: October 18, 2001Applicant: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Patent number: 6032265Abstract: A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.Type: GrantFiled: July 18, 1996Date of Patent: February 29, 2000Assignee: Hitachi, Ltd.Inventors: Hiroshi Oguro, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura
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Patent number: 6003116Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other.Type: GrantFiled: October 29, 1996Date of Patent: December 14, 1999Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Patent number: 5852728Abstract: The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.Type: GrantFiled: January 11, 1996Date of Patent: December 22, 1998Assignee: Hitachi, Ltd.Inventors: Koji Matsuda, Soichi Takaya, Yoshihiro Miyazaki, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa, Akira Yamagiwa, Masao Inoue, Kenji Kashiwagi
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Patent number: 5841963Abstract: A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.Type: GrantFiled: May 21, 1997Date of Patent: November 24, 1998Assignee: Hitachi, Ltd.Inventors: Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Hiroshi Ohguro
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Patent number: 5737513Abstract: A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.Type: GrantFiled: May 20, 1996Date of Patent: April 7, 1998Assignees: Hitachi, Ltd., Hitachi Information & Control Systems Inc.Inventors: Koji Matsuda, Yoshihiro Miyazaki, Soichi Takaya, Kazuhiro Hyuga, Nobuo Akeura, Shinichiro Yamaguchi, Naoto Miyazaki, Satoru Kayukawa
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Patent number: 5517669Abstract: A data communication system carries out transmission and reception of periodic data between a plurality of computers, and especially an improved data communication system which aims at more effective utilization of a system bus in each computer and which also aims at more effective utilization of a data transmission channel transmitting periodic data, so that the load imposed on the system bus during transfer of periodic data in each computer can be minimized, and the rate of occupation of the data transmission channel during transmission and reception of periodic data can also be minimized.Type: GrantFiled: March 16, 1994Date of Patent: May 14, 1996Assignee: Hitachi, Ltd.Inventors: Yoshinori Ohkura, Takuji Hamada, Shunji Inada, Shinichiro Yamaguchi, Hiroshi Tomizawa
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Patent number: 5146569Abstract: Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.Type: GrantFiled: March 25, 1991Date of Patent: September 8, 1992Assignee: Hitachi, Ltd.Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki
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Patent number: 5003458Abstract: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.Type: GrantFiled: October 23, 1987Date of Patent: March 26, 1991Assignee: Hitachi, Ltd.Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki
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Patent number: 4967339Abstract: A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.Type: GrantFiled: April 8, 1988Date of Patent: October 30, 1990Assignees: Hitachi, Ltd., Hitachi Engineering, Ltd.Inventors: Hiroaki Fukumaru, Soichi Takaya, Takayuki Morioka, Tadaaki Bandoh, Shinichiro Yamaguchi, Kenji Hirose
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Patent number: 4910081Abstract: A thermal transfer recording ink composition comprises a resin having a melting point according to JIS-K0064 of 55.degree. to 110.degree. C. and a solidification point according to JIS-K0064 being at least 50.degree. C. lower than the melting point, resin particles having a size of 0.05 to 2.0 microns and a coloring matter. It is coated on film and used repeatedly.Type: GrantFiled: September 14, 1988Date of Patent: March 20, 1990Assignee: Kao CorporationInventors: Shinichiro Yamaguchi, Shiro Kawahito, Hiroshi Yashima, Ryuma Mizushima
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Patent number: 4896258Abstract: A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.Type: GrantFiled: July 2, 1986Date of Patent: January 23, 1990Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hiroaki Nakanishi, Kenzi Hirose, Takao Kobayashi, Yoshihiro Miyazaki
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Patent number: 4841439Abstract: The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.Type: GrantFiled: October 14, 1986Date of Patent: June 20, 1989Assignee: Hitachi, Ltd.Inventors: Atsuhiko Nishikawa, Yoshihiro Miyazaki, Masayuki Tanji, Soichi Takaya, Shinichiro Yamaguchi
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Patent number: 4839846Abstract: An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).Type: GrantFiled: March 12, 1986Date of Patent: June 13, 1989Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi
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Patent number: 4811269Abstract: A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.Type: GrantFiled: October 8, 1986Date of Patent: March 7, 1989Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi
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Patent number: 4764869Abstract: Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.Type: GrantFiled: August 27, 1986Date of Patent: August 16, 1988Assignee: Hitachi, Ltd.Inventors: Yoshihiro Miyazaki, Soichi Takaya, Masayuki Tanji, Atsuhiko Nishikawa, Shinichiro Yamaguchi