Abstract: The present technology relates to a phase-locked loop that allows a reduction in power consumption. A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.

Abstract: An imaging element according to a first aspect includes: a successive approximation resistor type analog-digital converter that converts an analog signal output from a pixel including a photoelectric conversion part into a digital signal, in which the successive approximation resistor type analog-digital converter has a preamplifier having a band limiting function. An imaging element according to a second aspect includes a DAC in which the successive approximation resistor type analog-digital converter uses a capacitance element to convert a digital value after AD conversion to an analog value, and sets the analog value to a comparison reference for comparison with an analog input voltage.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

Abstract: A first successive approximation register analog-to-digital converter according an embodiment of the present disclosure includes an N-bit (N represents an integer greater than or equal to 5) capacitive digital-to-analog converter including a plurality of capacitive elements. A plurality of first capacitive elements of the plurality of capacitive elements is capacitive elements that have total capacity corresponding to total capacity of a plurality of the capacitive elements corresponding to a whole or a portion of first to (N?1)-th bits, and do not correspond to the first to (N?1)-th bits.

Abstract: The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.

Abstract: The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.