Abstract: A multi-system video signal demodulating apparatus includes at least a color signal processing unit and a color discriminating function for demodulating a component video signal from video signals of two or more different systems. The multi-system video signal demodulating apparatus includes a detector for detecting continuity between vertical synchronizing signals of the input video signals. The color discriminating function is executed when the detector detects a discontinuity between the vertical synchronizing signals. The continuity between the vertical synchronizing signals of the input video signals is detected. The color discriminating function is executed when a discontinuity between the vertical synchronizing signals is detected during continuity detection. A synchronizing signal of an input video signal is discriminated. A frequency of a color burst signal is discriminated based on a result of the synchronizing signal discrimination.

Abstract: An apparatus and method in which a difference between lines in an input composite video signal is calculated. The difference is compared with a specified threshold to detect chrominance correlation. A difference between lines in a composite video signal which is delayed for a one-frame period is calculated. The difference is compared with the specified threshold to detect chrominance correlation. The difference between these chrominance correlations is calculated and is used as a motion detection signal. When this frame difference is smaller than a specified threshold, the motion detection signal is forcibly set to 0.

Abstract: Chrominance signals of a digitized composite video signal are processed by including automatic phase control and automatic chroma control operations that use circuit elements that are concurrently available for both operations as well as for other signal processing operations. The automatic phase control operation calculates a phase error corresponding to a phase difference between a reference clock signal and a burst synchronization signal of the chrominance signal. The reference clock signal is generated in response to the phase error data, such that the phase error is minimized and the reference clock signal coincides with the burst synchronization signal. The automatic chroma control operation multiplies the chrominance signal by coefficient data corresponding to the difference between the chrominance signal and a reference value to generate a constant level chrominance signal.

Abstract: A noise shaping circuit in which the second significant bit of quantization input data in 2's complement representation, supplied to a quantizer, is taken out after complementation by an inverter 30, while the second significant bit and following bit or bits are taken out as such without complementation, for producing a quantization is error, which is subtracted from an input signal to render it possible to abbreviate an operation of finding the quantization error. A sole inverter may be used in substitution for a circuit portion employed for finding the quantization error for significantly diminishing the circuit scale.

Abstract: A raster distortion correcting signal synthesizer includes a multiplier, an adder, a memory for storing data and a coefficient, and a controller for controlling the multiplier, adder and memory in accordance with a count value of a horizontal sync. signal. The controller calculates a desired raster distortion correcting signal of a high order by utilizing the multiplier and adder on the basis of the count value, and multiplies the count value by a predetermined coefficient to obtain a new count value.

Abstract: A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.

Abstract: A correction signal generating circuit for a television receiver includes a counter for counting a pulse synchronized with a horizontal sync signal, a memory for storing correction data and a coefficient, and a unit for multiplying and adding contents of the counter and the memory. A signal feedback loop supplies an output from the multiplying and adding unit to an input thereof, and a control unit controls operation of the memory and the multiplying and adding unit, thereby generating a correction signal.