Patents by Inventor Shinichirou OOKI

Shinichirou OOKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system
    Patent number: 10852648
    Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyuki Hino, Hiromitsu Mashita, Masahiro Miyairi, Hiroshi Yoshimura, Taiga Uno, Sachiyo Ito, Shinichirou Ooki, Kenji Shiraishi, Hirotaka Ichikawa, Yuto Takeuchi
  • MASK PATTERN CORRECTION SYSTEM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD UTILIZING SAID CORRECTION SYSTEM
    Publication number: 20200117104
    Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 16, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyuki HINO, Hiromitsu MASHITA, Masahiro MIYAIRI, Hiroshi YOSHIMURA, Taiga UNO, Sachiyo ITO, Shinichirou OOKI, Kenji SHIRAISHI, Hirotaka ICHIKAWA, Yuto TAKEUCHI