Abstract: A measurement apparatus measuring a flight time of a search wave corresponding to a time after the search wave is emitted and before a reflected wave is received is provided. The measurement apparatus includes a transceiver, a memory portion, a sampling portion, a measurement portion, and a determination portion. The transceiver emits the search wave and receives the reflected wave. The sampling portion generates a sampling data and causes the memory portion to store the sampling data. The sampling portion includes a first processing unit and a second processing unit. The first processing unit causes the memory portion to store the sampling data as a first signal data. The second processing unit causes the memory portion to store the sampling data as a second signal data. The measurement portion measures the flight time and generates a measurement value of the flight time. The determination portion determines a sampling period.

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract: A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D?W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed.

Abstract: A communication system includes a communication wiring, at least one master node connected to the communication wiring, and at least one slave node connected to the communication wiring. The at least one master node and the at least one slave node are connected in a ring shape through the communication wiring and communicate in a start-stop synchronous communication.

Abstract: A measurement apparatus measuring a flight time of a search wave corresponding to a time after the search wave is emitted and before a reflected wave is received is provided. The measurement apparatus includes a transceiver, a memory portion, a sampling portion, a measurement portion, and a determination portion. The transceiver emits the search wave and receives the reflected wave. The sampling portion generates a sampling data and causes the memory portion to store the sampling data. The sampling portion includes a first processing unit and a second processing unit. The first processing unit causes the memory portion to store the sampling data as a first signal data. The second processing unit causes the memory portion to store the sampling data as a second signal data. The measurement portion measures the flight time and generates a measurement value of the flight time. The determination portion determines a sampling period.

Abstract: Between a CPU and a communication module, a write buffer, a write control section, a read buffer and a read control section are provided. The CPU directly accesses and the write buffer and the read buffer. By periodically outputting a communication request, the read control section reads data, which the communication module received from other nodes, and transfers the data to the read buffer. The write control section transfers to the communication module the data written in the write buffer as transmission data. In addition, a bypass access control section and an access sequence control section are provided. The bypass access control section controls direct data read and data write between the CPU and the communication module. The access sequence control section controls sequence of accesses of the control sections to the communication module.

Abstract: A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D?W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed.

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract: Between a CPU and a communication module, a write buffer, a write control section, a read buffer and a read control section are provided. The CPU directly accesses and the write buffer and the read buffer. By periodically outputting a communication request, the read control section reads data, which the communication module received from other nodes, and transfers the data to the read buffer. The write control section transfers to the communication module the data written in the write buffer as transmission data. In addition, a bypass access control section and an access sequence control section are provided. The bypass access control section controls direct data read and data write between the CPU and the communication module. The access sequence control section controls sequence of accesses of the control sections to the communication module.

Abstract: A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

Abstract: A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.

Abstract: A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.

Abstract: A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

Abstract: A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.

Abstract: A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.