Patents by Inventor Shinitirou Hayashi

Shinitirou Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6126752
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6080617
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 5717233
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: February 10, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki