Patents by Inventor Shinji Aono

Shinji Aono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5850088
    Abstract: This invention provides TEGs for improving accuracy of lifetime evaluation. The TEGs include a base region <Ba> selectively having a cathode region <C> in the surface portion thereof, and an anode region <A>. The intersection of a center line of the cathode region <C> and the anode region <A> provides a function region <WT> located within the range of 5h, five times as much as a height h of a wafer <W>. The function region <WT> makes a pair with the cathode region <C> and actually serves as an actual anode region for the cathode region <C>. As an area ratio of the cathode region <C> to the function region <WT> is smaller, ON voltage values Vf obtained for respective lifetime values get isolated from each other. Thus, the cathode region <C> is formed so that the area ratio of the cathode region <C> to the function region <WT> is about 1/1750000 to 1/4500.
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: December 15, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinji Aono
  • Patent number: 5751023
    Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device is provided with an n.sup.+ -type layer located between an n-type buffer layer and a p-type collector layer and having a higher impurity concentration than n-type buffer layer. A diffusion depth of p-type collector layer toward a first main surface is smaller in a first region and is larger in a second region. As a result, the semiconductor device has a sufficiently reduced turn-off loss.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: May 12, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinji Aono
  • Patent number: 5738571
    Abstract: An apparatus and method for forming at least one of a rib and groove on a surface of a power transmission belt/belt sleeve. The apparatus has first and second supports on which the belt/belt sleeve can be mounted for movement in an endless path. First structure is provided on at least one of the first and second supports for reinforcing a belt/belt sleeve, mounted on the first and second supports, against movement and deformation of the belt/belt sleeve relative to the at least one of the first and second supports transversely to the endless path as the belt/belt sleeve moves in the endless path.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: April 14, 1998
    Assignee: Mitsuboshi Belting Ltd.
    Inventors: Koji Kitahama, Yuji Okiyoshi, Masahiko Kawashima, Shinji Aono, Osamu Miyajima
  • Patent number: 5382926
    Abstract: A loaded line phase shifter includes a semiconductor substrate; a main transmission line one-quarter wavelength long disposed on the semiconductor substrate; loaded lines connected to opposite ends of the main line; first and second FETs with drain electrodes connected to the other ends of the loaded lines and grounded source electrodes; and a resonant circuit including a third FET and an inductor connected between the drain electrodes of said first and second FETs. A desired phase shift quantity of the phase shifter is determined by the characteristic impedance of the main line, the reactance components of the loaded lines, and the off-capacitances of the FETs. When the resonant circuit is closed in this structure, the susceptance of the loaded lines and the first and second FETs is equal to zero, resulting in a phase shift quantity equivalent to half of the phase shift quantity obtained when the resonant circuit is opened.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: January 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiko Nakahara, Shinji Aono