Abstract: The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein the graphite comprises hexagonal crystal graphite and rhombohedral crystal graphite, and has a low-crystalline carbon coating on a surface thereof; and the graphite has exothermic peaks in the range of 600° C. or lower and in the range of 690° C. or higher in DTA measurement, or the graphite has a full width at half maximum of a (101) peak of the hexagonal crystal graphite of 0.2575° or less in XRD measurement, or the graphite has an absolute value of the difference between the lattice strain obtained from (101) plane spacing of the hexagonal crystal graphite and the lattice strain obtained from (100) plane spacing of the hexagonal crystal graphite of 7.1×10?4 or less in XRD measurement.

Abstract: An object is to provide means, which is capable of performing quality management with sufficient precision even in a case where the thickness of an amorphous carbon layer is small, as quality management means for a negative electrode active material of a lithium-ion secondary battery including an amorphous carbon layer on a surface. Provided is a quality management method for a negative electrode active material of a lithium-ion secondary battery which includes an amorphous carbon layer on a surface. In the quality management method, an aspect of a change in a plurality of D/G ratios, which are obtained by performing a first process of heating an inspection object at a predetermined heating temperature, and of measuring each of the D/G ratios through Raman scattering spectroscopy measurement a predetermined number of times while changing the heating temperature, is set as an index of the quality management.

Abstract: The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein the graphite comprises hexagonal crystal graphite and rhombohedral crystal graphite, and has a low-crystalline carbon coating on a surface thereof; and the graphite has exothermic peaks in the range of 600° C. or lower and in the range of 690° C. or higher in DTA measurement, or the graphite has a full width at half maximum of a (101) peak of the hexagonal crystal graphite of 0.2575° or less in XRD measurement, or the graphite has an absolute value of the difference between the lattice strain obtained from (101) plane spacing of the hexagonal crystal graphite and the lattice strain obtained from (100) plane spacing of the hexagonal crystal graphite of 7.1×10?4 or less in XRD measurement.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.

Abstract: A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.

Abstract: A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Abstract: A field effect transistor available for 1 giga-bit dynamic random access memory device has a two-layer gate structure consisting of a lower layer of nitrogen-containing silicon and an upper layer of refractory metal, and the nitrogen-containing silicon effectively prevents the gate oxide layer from alkaline metals diffused from the refractory metal.