Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first semiconductor type, a first semiconductor layer of the first semiconductor type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first semiconductor type, trenches, a gate insulating film, and gate electrodes. The silicon carbide semiconductor device has a minimum value of a subthreshold slope factor (subthreshold swing) in a subthreshold region in a range from 0.24V/dec. to 0.3V/dec.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Abstract: The present invention provides a photovoltaic module with bypass diodes that has a high electricity generating capacity per unit area and high productivity. This photovoltaic module includes a photovoltaic cell assembly in which a plurality of photovoltaic cells are electrically connected in series, and a diode assembly in which a plurality of diodes are formed on a substrate in the arrangement that is consistent with the arrangement of the photovoltaic cells to which the diodes are to be attached. The diode assembly is disposed on a non-light receiving side of the photovoltaic cells, and the diodes are electrically connected to the photovoltaic cells. The photovoltaic cell assembly and the diode assembly are sealed and united by a sealant.

Abstract: The present invention provides a photovoltaic module with bypass diodes that has a high electricity generating capacity per unit area and high productivity. This photovoltaic module includes a photovoltaic cell assembly in which a plurality of photovoltaic cells are electrically connected in series, and a diode assembly in which a plurality of diodes are formed on a substrate in the arrangement that is consistent with the arrangement of the photovoltaic cells to which the diodes are to be attached. The diode assembly is disposed on a non-light receiving side of the photovoltaic cells, and the diodes are electrically connected to the photovoltaic cells. The photovoltaic cell assembly and the diode assembly are sealed and united by a sealant.

Abstract: A method is disclosed for manufacturing a thin film substrate solar cell that has a metal electrode, a photoelectric conversion layer, and a transparent electrode stacked in this order on a substrate, the photoelectric conversion layer combining, in a thickness direction, two or more n, i, p junctions with non-single crystal silicon as main materials thereof. A top cell which is the photoelectric conversion layer on the side of the transparent electrode and another cell of one or more layers on the side of the metal electrode relative to the top cell are provided. The method includes a step of simultaneously removing at least the two or more photoelectric conversion layers and the transparent electrode using a laser with a wavelength having selective sensitivity with respect to the top cell, from the side of the transparent electrode, followed by blowing-away.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A method of evaluating a thickness of a film during a polishing process includes the steps of irradiating light onto a surface of the film during the polishing process; obtaining a differential signal of reflection spectra at a polishing time t and a polishing time t??t with a time difference ?t from the polishing time t; and analyzing the differential signal to obtain a thickness d of the film at the polishing time t.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A method of evaluating a thickness of a film during a polishing process includes the steps of irradiating light onto a surface of the film during the polishing process; obtaining a differential signal of reflection spectra at a polishing time t and a polishing time t??t with a time difference ?t from the polishing time t; and analyzing the differential signal to obtain a thickness d of the film at the polishing time t.

Abstract: The film thickness of a p-type semiconductor was adjusted in order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage. In order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage, it was also shown to be favorable to control acceptor impurity levels in p-type semiconductors. Irradiation conditions of more than 10 hours at 1 SUN or (light intensity [SUN])2×10 or more (time [h])>10 were utilized.

Abstract: Solar cells are formed of (a) a transparent substrate; (b) a transparent electrode; (c) a first doped layer comprising amorphous silicon oxide, optionally including nitrogen, said first doped layer containing a dopant whereby the first doped layer is of a first conductivity type and has an optical gap of from 2.0 to 2.3 eV and a ratio of light conductivity to dark conductivity of 5 or less at 25.degree. C.; (d) a layer of intrinsic amorphous silicon; (e) a second doped layer comprising amorphous silicon, said second doped layer containing a dopant whereby the second doped layer is of a second conductivity type different from the first conductivity type; and (f) a second electrode. The first doped layer may be of either n-type or p-type conductivity. The first doped layer can be formed over the transparent electrode by decomposing a gas mixture comprising SiH.sub.4, an oxygen source gas selected from N.sub.2 O or CO.sub.2, and a dopant, in a hydrogen carrier at a substrate temperature of 150.degree. to 250.