Abstract: A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors from the data holding circuits. This keeps the number of buffer circuits inserted between the data holding circuits small and shortens the processing time required for correcting the hold error.

Abstract: When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal corresponding to a signal terminal designated for input level fixation by the circuit connectivity information on the basis of terminal correspondence information, a second step of specifying a power supply voltage corresponding to the power supply terminal specified at the first step on the basis of the power supply information, and a third step of routing a power supply line of the power supply voltage specified at the second step to the signal terminal for input level fixation and thus connecting them, are carried out. Thus, connection processing to connect the signal terminal for input level fixation and the power supply line can be automatically carried out and a design period for a multi-power supply semiconductor integrated circuit can be reduced.

Abstract: A method for generating layout data for macro cells in a core region of a semiconductor device. The method includes generating wiring margin-added macro cells, calculating the area of a maximum standard cell region by excluding the area of the wiring margin-added macro cells from the area of the core region, calculating the area of an actual standard cell region in which layout of standard cells is enabled in the core region in accordance with a floor plan laying out the wiring margin-added macro cells, calculating a dead space percentage of the floor plan from the area of the maximum standard cell region and the area of the actual standard cell region, and correcting the floor plan by moving at least one wiring margin-added macro cells so that the dead space percentage becomes less than a reference value.

Abstract: A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors from the data holding circuits. This keeps the number of buffer circuits inserted between the data holding circuits small and shortens the processing time required for correcting the hold error.

Abstract: A method for generating layout data for macro cells in a core region of a semiconductor device. The method includes generating wiring margin-added macro cells, calculating the area of a maximum standard cell region by excluding the area of the wiring margin-added macro cells from the area of the core region, calculating the area of an actual standard cell region in which layout of standard cells is enabled in the core region in accordance with a floor plan laying out the wiring margin-added macro cells, calculating a dead space percentage of the floor plan from the area of the maximum standard cell region and the area of the actual standard cell region, and correcting the floor plan by moving at least one wiring margin-added macro cells so that the dead space percentage becomes less than a reference value.

Abstract: When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal corresponding to a signal terminal designated for input level fixation by the circuit connectivity information on the basis of terminal correspondence information, a second step of specifying a power supply voltage corresponding to the power supply terminal specified at the first step on the basis of the power supply information, and a third step of routing a power supply line of the power supply voltage specified at the second step to the signal terminal for input level fixation and thus connecting them, are carried out. Thus, connection processing to connect the signal terminal for input level fixation and the power supply line can be automatically carried out and a design period for a multi-power supply semiconductor integrated circuit can be reduced.

Abstract: A semiconductor device that facilitates the layout designing of cells and power supply lines. The semiconductor device includes a first power supply line that corresponds to a first power supply voltage, a second power supply line that corresponds to a second power supply voltage, and a function block. A first standard cell is arranged in the function block and has a first power supply terminal connected to the first power supply line. A second standard cell has a second power supply terminal connected to the second power supply line. A level converter cell is aligned with the first and second standard cells and has a third power supply terminal connected to the first power supply line and a fourth power supply terminal connected to the second power supply line.

Abstract: In a semiconductor device having a multiple layer wiring structure, a wiring method, a wiring device, and a recording medium, by optimizing the placement of SVIA, it is possible, for an intersection portion where a lower metal wiring layer having a width W1 and an upper metal wiring layer having a width W4 intersect with the intermediate metal layers sandwiched in between, to delete one row in the X direction and two rows in the Y direction for a total of nine SVIAs, when five SVIAs are arranged at the pitch PX in the X direction (i.e. in the transverse direction of the upper metal wiring layer) and three SVIAs are arranged at the pitch PY in the Y direction (i.e. in the transverse direction of the lower metal wiring layer) for a total of fifteen SVIAs. As a result, it is possible to secure one wiring track through which wiring is able to pass from among the three wiring tracks in the X direction and two wiring tracks through which wiring is able to pass from among the five wiring tracks in the Y direction.

Abstract: In a semiconductor device having a multiple layer wiring structure, a wiring method, a wiring device, and a recording medium, by optimizing the placement of SVIA, it is possible, for an intersection portion where a lower metal wiring layer having a width W1 and an upper metal wiring layer having a width W4 intersect with the intermediate metal layers sandwiched in between, to delete one row in the X direction and two rows in the Y direction for a total of nine SVIAs, when five SVIAs are arranged at the pitch PX in the X direction (i.e. in the transverse direction of the upper metal wiring layer) and three SVIAs are arranged at the pitch PY in the Y direction (i.e. in the transverse direction of the lower metal wiring layer) for a total of fifteen SVIAS. As a result, it is possible to secure one wiring track through which wiring is able to pass from among the three wiring tracks in the X direction and two wiring tracks through which wiring is able to pass from among the five wiring tracks in the Y direction.

Abstract: A semiconductor device that facilitates the layout designing of cells and power supply lines. The semiconductor device includes a first power supply line that corresponds to a first power supply voltage, a second power supply line that corresponds to a second power supply voltage, and a function block. A first standard cell is arranged in the function block and has a first power supply terminal connected to the first power supply line. A second standard cell has a second power supply terminal connected to the second power supply line. A level converter cell is aligned with the first and second standard cells and has a third power supply terminal connected to the first power supply line and a fourth power supply terminal connected to the second power supply line.

Abstract: In a semiconductor device having a multiple layer wiring structure, a wiring method, a wiring device, and a recording medium, by optimizing the placement of SVIA, it is possible, for an intersection portion where a lower metal wiring layer having a width W1 and an upper metal wiring layer having a width W4 intersect with the intermediate metal layers sandwiched in between, to delete one row in the X direction and two rows in the Y direction for a total of nine SVIAs, when five SVIAs are arranged at the pitch PX in the X direction (i.e. in the transverse direction of the upper metal wiring layer) and three SVIAs are arranged at the pitch PY in the Y direction (i.e. in the transverse direction of the lower metal wiring layer) for a total of fifteen SVIAs. As a result, it is possible to secure one wiring track through which wiring is able to pass from among the three wiring tracks in the X direction and two wiring tracks through which wiring is able to pass from among the five wiring tracks in the Y direction.