Patents by Inventor Shinji Hatae

Shinji Hatae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10494390
    Abstract: An organic magnesium phosphide expressed by Formula (1) below and an organic magnesium phosphide complex expressed by Formula (9) below are provided, and a manufacturing method of organic phosphorus compound is characterized in that the above compounds used as a reagent is reacted with an electrophile: wherein R1 and R2 are each independently an aliphatic group, heteroaliphatic group, alicyclic group, or heterocyclic group, and X is chlorine, bromine, or iodine, wherein R3 and R4 are each independently an aliphatic group, heteroaliphatic group, aromatic group, alicyclic group, or heterocyclic group, and X and Y are each independently chlorine, bromine, or iodine.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 3, 2019
    Assignee: HOKKO CHEMICAL INDUSTRY CO., LTD.
    Inventors: Kenta Suzuki, Nobumichi Kumamoto, Nobuhiro Ito, Shinji Hatae, Hiroyuki Suzuki
  • Publication number: 20190248815
    Abstract: An organic magnesium phosphide expressed by Formula (1) below and an organic magnesium phosphide complex expressed by Formula (9) below are provided, and a manufacturing method of organic phosphorus compound is characterized in that the above compounds used as a reagent is reacted with an electrophile: wherein R1 and R2 are each independently an aliphatic group, heteroaliphatic group, alicyclic group, or heterocyclic group, and X is chlorine, bromine, or iodine, wherein R3 and R4 are each independently an aliphatic group, heteroaliphatic group, aromatic group, alicyclic group, or heterocyclic group, and X and Y are each independently chlorine, bromine, or iodine.
    Type: Application
    Filed: June 29, 2017
    Publication date: August 15, 2019
    Inventors: Kenta SUZUKI, Nobumichi KUMAMOTO, Nobuhiro ITO, Shinji HATAE, Hiroyuki SUZUKI
  • Patent number: 10017534
    Abstract: The present invention relates to a method for producing a Tebbe complex having high purity and high activity and having excellent storage stability in a high yield, the method including allowing bis(cyclopentadienyl)titanium dichloride and trimethylaluminum to react with each other in the presence of a solvent such that a solubility of the Tebbe complex in 1 g of the solvent at 25° C. is 0.5 mmol/g or less.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 10, 2018
    Assignee: KURARAY CO., LTD.
    Inventors: Shinji Hatae, Syuichi Sunaga, Tomoaki Tsuji
  • Publication number: 20170218002
    Abstract: The present invention relates to a method for producing a Tebbe complex having high purity and high activity and having excellent storage stability in a high yield, the method including allowing bis(cyclopentadienyl)titanium dichloride and trimethylaluminum to react with each other in the presence of a solvent such that a solubility of the Tebbe complex in 1 g of the solvent at 25° C. is 0.5 mmol/g or less.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 3, 2017
    Applicant: KURARAY CO., LTD
    Inventors: Shinji HATAE, Syuichi SUNAGA, Tomoaki TSUJI
  • Patent number: 8970186
    Abstract: A voltage conversion circuit apparatus that adjusts a timing skew between the switching control of the first switching element and the switching control of the second switching element includes: a skew storage portion that stores a timing skew between the switching controls of the first and second switching elements after the voltage conversion circuit apparatus is manufactured; and a timing adjustment portion that corrects the stored timing skew and thereby adjusts the timing relation between a first pulse signal and a second pulse signal so as to bring within a permissible range the timing skew that occurs when the switching controls of the first and second switching elements are performed by using the first pulse signal and the second pulse signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 3, 2015
    Assignees: Toyota Jidosha Kabushiki Kaisha, Mitsubishi Electric Corporation
    Inventors: Kota Manabe, Takahiko Hasegawa, Tomohiko Kaneko, Khalid Hassan Hussein, Shinji Hatae
  • Patent number: 8614566
    Abstract: Provided is a DC-DC converter capable of reducing not only a turn-off loss but also a turn-on loss. A snubber capacitor has one end connected to an anode of a step-up diode, a current input end of a step-up switching element and a main reactor. A first snubber diode has a cathode connected to other end of the snubber capacitor, and an anode connected to a cathode of the step-up diode. A second snubber diode has an anode connected to the cathode of the first snubber diode and other end of the snubber capacitor. A snubber reactor has one end connected to the anode of the first snubber diode, and other end connected to a cathode of the second snubber diode.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 24, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Hatae, Khalid Hassan Hussein
  • Publication number: 20130119968
    Abstract: A voltage conversion circuit apparatus that adjusts a timing skew between the switching control of the first switching element and the switching control of the second switching element includes: a skew storage portion that stores a timing skew between the switching controls of the first and second switching elements after the voltage conversion circuit apparatus is manufactured; and a timing adjustment portion that corrects the stored timing skew and thereby adjusts the timing relation between a first pulse signal and a second pulse signal so as to bring within a permissible range the timing skew that occurs when the switching controls of the first and second switching elements are performed by using the first pulse signal and the second pulse signal.
    Type: Application
    Filed: June 1, 2011
    Publication date: May 16, 2013
    Applicants: MITSUBISHI ELECTRIC CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kota Manabe, Takahiko Hasegawa, Tomohiko Kaneko, Khalid Hassan Hussein, Shinji Hatae
  • Publication number: 20120068678
    Abstract: Provided is a DC-DC converter capable of reducing not only a turn-off loss but also a turn-on loss. A snubber capacitor has one end connected to an anode of a step-up diode, a current input end of a step-up switching element and a main reactor. A first snubber diode has a cathode connected to other end of the snubber capacitor, and an anode connected to a cathode of the step-up diode. A second snubber diode has an anode connected to the cathode of the first snubber diode and other end of the snubber capacitor. A snubber reactor has one end connected to the anode of the first snubber diode, and other end connected to a cathode of the second snubber diode.
    Type: Application
    Filed: July 14, 2011
    Publication date: March 22, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shinji HATAE, Khalid Hassan HUSSEIN
  • Patent number: 7235857
    Abstract: A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to extend from the front surface to the back surface of the substrate, and first and second MOSFETs formed on opposite sides of the isolating region, respectively.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: June 26, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Shinji Hatae, Akihisa Yamamoto
  • Patent number: 7148562
    Abstract: A plurality of power semiconductor chips (power transistors or the like) are arranged, being separated from each other with a free space of a terminal board interposed therebetween. A radiating block is in contact with an insulating layer (a package and grease below the terminal board) below an arrangement region of each of the power semiconductor devices and a region between power semiconductor devices, and this increases a heat dissipation effect. With this construction, it is possible to provide a power semiconductor device and a power semiconductor module which ensure an excellent dissipation effect of heat radiated in operation of the power semiconductor chips.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: December 12, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takanobu Yoshida, Shinji Hatae
  • Publication number: 20050093123
    Abstract: A plurality of power semiconductor chips (power transistors or the like) are arranged, being separated from each other with a free space of a terminal board interposed therebetween. A radiating block is in contact with an insulating layer (a package and grease below the terminal board) below an arrangement region of each of the power semiconductor devices and a region between power semiconductor devices, and this increases a heat dissipation effect. With this construction, it is possible to provide a power semiconductor device and a power semiconductor module which ensure an excellent dissipation effect of heat radiated in operation of the power semiconductor chips.
    Type: Application
    Filed: June 22, 2004
    Publication date: May 5, 2005
    Inventors: Takanobu Yoshida, Shinji Hatae
  • Patent number: 6762491
    Abstract: The present invention is to provide a power semiconductor device including a heat radiator having a principal surface and an insulating substrate bonded on the principal surface of the heat radiator via a first solder layer. The power semiconductor device also includes at least one semiconductor chip mounted on the insulating substrate via a second solder layer. The insulating substrate has a thin-layer and thick-layer edges, and is bonded on the principal surface of the heat radiator so that the first solder layer has a thickness thinner towards a direction from the thin-layer edge to the thick-layer edge (T1>T2). Also, the semiconductor chip is mounted on the insulating substrate so that a first distance between the thick-layer edge and the semiconductor chip is less than a second distance between the thin-layer edge and the semiconductor chip (L1<L2).
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: July 13, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Hatae, Korehide Okamoto
  • Patent number: 6724169
    Abstract: A controller for controlling a power device in response to an input signal includes a first signal generator for generating a first signal in response to the input signal; a level shifter for changing an output level of the first signal to a value which is a function of a first main power supply potential in order to produce a second signal; and a first control signal generator for generating the control signal for a first semiconductor device in response to the second signal. The level shifter includes at least one level shifting semiconductor element wherein the semiconductor element is controlled by the first signal and the at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of the first and a value of a second main power supply potential.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: April 20, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Shinji Hatae, Tatsuo Oota, Masanori Fukunaga
  • Publication number: 20040070047
    Abstract: A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to extend from the front surface to the back surface of the substrate, and first and second MOSFETs formed on opposite sides of the isolating region, respectively.
    Type: Application
    Filed: August 20, 2003
    Publication date: April 15, 2004
    Inventors: Gourab Majumdar, Shinji Hatae, Akihisa Yamamoto
  • Patent number: 6643155
    Abstract: It is an object of the present invention to provide an inverter circuit including a power arm ensuring a high breakdown voltage and having low probability of malfunction. In a power arm element consisting of a switching element and a diode connected in inverse-parallel connection thereto, n free wheeling diodes (n≧2) connected in series are connected in inverse-parallel connection to a switching element (1b). A breakdown voltage between an anode and a cathode of each free wheeling diode is defined to be 1/n of a breakdown voltage of the switching element (1b). That is, the breakdown voltage of each free wheeling diode is reduced to 1/n to reduce a thickness of a n− drift region. A transient voltage characteristic during flow of a free wheeling current can be thereby kept low. The drop in the breakdown voltage is compensated with the n free wheeling diodes connected in series, to thereby ensure breakdown voltage of a degree approximately the same as that of the switching element.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: November 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Shinji Hatae
  • Patent number: 6639295
    Abstract: In a semiconductor substrate, semiconductor regions belonging to the IGBT are formed in an IGBT region and semiconductor regions belonging to the diode are formed in a diode region. The IGBT and the diode are connected in anti-parallel to each other. A trench in which an insulator is buried is formed between the IGBT region and the diode region. The insulator restricts the reverse recovery current which flows from the diode region into the IGBT region. Thus, semiconductor regions of an IGBT and a diode connected in anti-parallel with each other are fabricated in a single semiconductor substrate and the chip size is reduced.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: October 28, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Shinji Hatae, Akihisa Yamamoto
  • Patent number: 6529062
    Abstract: A power module is provided with an insulating substrate with a heat sink being bonded to one surface thereof and a circuit pattern being formed on the other surface. The circuit pattern is formed by an electrode layer. A switching semiconductor element and a free wheeling diode that is connected to a switching semiconductor element in anti-parallel therewith are placed on the circuit pattern. A controlling IC for controlling the switching semiconductor element is placed on the free wheeling diode. Thus, it is possible to make the entire power module compact, and it becomes possible to provide an inexpensive power module which can prevent the controlling IC from malfunctioning due to heat generated by the switching semiconductor element.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: March 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Mitsutaka Iwasaki, Shinji Hatae, Fumitaka Tametani, Toru Iwagami, Akihisa Yamamoto
  • Patent number: 6522098
    Abstract: A semiconductor device comprising at least one power device, at least one control element for controlling the power device(s), a plurality of first terminals connected to the power device(s), a plurality of second terminals connected to the control element(s), a support member having a heat sink disposed on a lower surface of the support member and the power device(s), control element(s), and first and second terminals arranged on the upper surface of the support member, and a package including the support member for sealing the devices and one end of the terminals such that first and second terminals protrude from different sides of the package. The arrangement allows a reduced size three-phase motor drive controller, a reduction in noise interference to the control element, and reduction in terminal pitch size.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: February 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Gourab Majumdar, Shinji Hatae, Tatsuo Oota, Masanori Fukunaga
  • Publication number: 20030030394
    Abstract: A controller for power devices which is not required to individually insulate high and low potential portions and to include an insulated power supply is disclosed. An external controller (6) is connected to a second internal control circuit (4) which is in turn connected to a level shift circuit (5) and a gate electrode of a transistor (Q2). Power supply voltage (V1) is applied to the second internal control circuit (4) for operation thereof. The level shift circuit (5) is connected to a first internal control circuit (3) which is in turn connected to a gate electrode of a transistor (Q1) and a charge pump circuit (7). Control of a first semiconductor circuit is made through the level shift means in response to an input signal generated on the basis of a second main power supply potential, thereby achieving increased responsiveness of the power devices to a control signal and improved integration.
    Type: Application
    Filed: October 1, 2002
    Publication date: February 13, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Gourab Majumdar, Shinji Hatae, Tatsuo Oota, Masanori Fukunaga
  • Publication number: 20020153586
    Abstract: In a semiconductor substrate (100), semiconductor regions (1, 2, 3, 5) belonging to the IGBT are formed in an IGBT region (20) and semiconductor regions (1, 4) belonging to the diode are formed in a diode region (21). The IGBT and the diode are connected in anti-parallel to each other. A trench (15) in which an insulator (16) is buried is formed between the IGBT region (20) and the diode region (21). The insulator (16) restricts the reverse recovery current which flows from the diode region (21) into the IGBT region (20). Thus, semiconductor regions of an IGBT and a diode connected in anti-parallel with each other are fabricated in a single semiconductor substrate and the chip size is reduced.
    Type: Application
    Filed: September 18, 2001
    Publication date: October 24, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Gourab Majumdar, Shinji Hatae, Akihisa Yamamoto