Abstract: Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.

Abstract: A semiconductor device according to the present invention comprises, on a first semiconductor chip, a first circuit element region in which a first electrode group is arranged along an outer periphery of the first semiconductor chip in such a manner as to surround a second semiconductor chip, a second electrode group is arranged along the outer periphery of the first semiconductor chip in such a manner as to surround the first electrode group, and the first semiconductor chip is surrounded by the first electrode group, and a second circuit element region which surrounds the first electrode group and is surrounded by the second electrode group.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: A serial bus data control device for communication devices to receive data in a packet format is provided which is capable of obtaining each piece of actual data contained in each of packets needed for reconstructing a series of original data by storing actual data contained in two or more received packets in a memory location with a continued address in a buffer. The serial bus data control device includes a preprocessing section to recognize each of the packets received through the serial bus and to divide the actual data contained in each of the packets into a plurality of unit length data portions having a predetermined length, and a storing section to store the actual data portions contained in each of the packets recognized by the preprocessing section. The preprocessing section has an address control circuit to perform addressing to store each of the unit length data constituting the actual data contained in each of the packets.

Abstract: A semiconductor device according to the present invention comprises, on a first semiconductor chip, a first circuit element region in which a first electrode group is arranged along an outer periphery of the first semiconductor chip in such a manner as to surround a second semiconductor chip, a second electrode group is arranged along the outer periphery of the first semiconductor chip in such a manner as to surround the first electrode group, and the first semiconductor chip is surrounded by the first electrode group, and a second circuit element region which surrounds the first electrode group and is surrounded by the second electrode group.

Abstract: A serial bus data control device for communication devices to receive data in a packet format is provided which is capable of obtaining each piece of actual data contained in each of packets needed for reconstructing a series of original data by storing actual data contained in two or more received packets in a memory location with a continued address in a buffer. The serial bus data control device includes a preprocessing section to recognize each of the packets received through the serial bus and to divide the actual data contained in each of the packets into a plurality of unit length data portions having a predetermined length, and a storing section to store the actual data portions contained in each of the packets recognized by the preprocessing section. The preprocessing section has an address control circuit to perform addressing to store each of the unit length data constituting the actual data contained in each of the packets.

Abstract: Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.

Abstract: A process controller 130 and clock controller 190 are used to detect transfer rates when performing data write and read operations involving memories 180-1 to 180-n for recording data. The clock controller 190 frequency-divides clock signals generated by an oscillator unit 191, thereby generating a plurality of frequency-divided clocks having different frequencies. One of the frequency-divided clocks is selected, according to the transfer rate detection results, and used as the operating clock for an interface unit 110, the process controller 130, a buffer unit 140, and a transfer controller 150. By altering the operating speeds of the circuits 110, 140, and 150, according to the data transfer rate, power consumption can be reduced.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n-1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n-1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: A storage device uses an inventive alternate processing method for accommodating defective sectors of the storage device. The storage device includes a host interface, an alternate process controller which controls the storage and transfer of user data in and among the components of the apparatus, a memory which has a user sector area, an alternate information area, and a spare sector area, and a buffer memory which may be a part of the controller. User data addressed to normal sectors of memory are stored directly in the user sector area. When user data is addressed to a defective sector, the controller performs alternate processing and temporarily stores the data in the buffer memory. A plurality of user data sectors stored in the buffer memory are then written by the controller at one time to the spare sector area of memory using address data in the alternate information area.

Abstract: The aim is to improve reliability and life of a semiconductor storage device using memory elements for which deterioration is a problem. In a semiconductor disk device equipped with a flash memory section 110 having memory elements M(0).about.M(9) having a plurality of sectors used as ordinary sectors or spare sectors, and a disk controller section 120 that performs data writing/reading in respect of memory elements M(0).about.M(9) in accordance with address information input from outside, there are provided a data error information management table 127 that stores for each memory element the situation regarding occurrence of write/read error of memory elements M(0).about.M(9), a micro CPU 131 that detects deterioration of memory elements in accordance with the situation regarding occurrence of write/read error stored in data error information management table 127, and an address conversion table 128 that effects conversion of address information such that memory elements M(0).about.

Abstract: A method for calculating the remaining life of a semiconductor disk device including a step for calculating the number of sectors remained employable in the reserve area, a step for calculating the number of sectors which have been fully employed and the number of sectors which are under employment, the sectors being contained in the reserve area, a step for calculating a ratio of a sum of the number of sectors which have been fully employed and the number of sectors which are under employment and the number of sectors remained employable, and a step for calculating the remaining life of the semiconductor disk device employing the ratio.