Patents by Inventor Shinji Inoue

Shinji Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063889
    Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROHARU JINMURA, YOSHIHIRO NAKADA, AKIRA INOUE, TAKESHI YANEDA
  • Publication number: 20250056965
    Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate, a light-emitting element layer provided on the thin-film transistor layer, and a sealing film provided on the light-emitting element. Each of light-emitting elements includes: a first electrode; a functional layer, and a second electrode stacked on top of another in a stated order. The display device includes: a display region; a frame region; and a non-display region. The non-display region includes a through hole. The display device includes a separation wall shaped into a frame and provided to the non-display region along an edge of the through hole. The separation wall includes: a first resin layer, and a first metal layer provided on the first resin layer. The first metal layer includes a first protrusion shaped into a canopy, and protruding from the first resin layer toward the display region.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, RYOSUKE GUNJI, SHINJI ICHIKAWA, HIROHARU JINMURA, AKIRA INOUE, YOSHIHIRO NAKADA
  • Publication number: 20250046612
    Abstract: The reliability of a semiconductor device is improved. In this disclosure, a gate insulating film is formed on a silicon carbide semiconductor substrate in a process using a material gas containing a halogen element and a metal element by an ALD method.
    Type: Application
    Filed: July 18, 2024
    Publication date: February 6, 2025
    Inventors: Tadashi YAMAGUCHI, Shinji INOUE
  • Patent number: 12140219
    Abstract: A waterproof structure for a speed reducer according to one aspect of the disclosure includes: a speed reducer for decelerating a rotational driving force of an electric motor and transmitting the decelerated rotational driving force to a rotationally driven portion; a motor flange housing the speed reducer; a cover externally covering the speed reducer in a liquid-tight manner; and a holding plate and a first fixing bolt provided on an inner peripheral side of the cover to fix the cover to the motor flange.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: November 12, 2024
    Assignee: NABTESCO CORPORATION
    Inventors: Shinji Inoue, Ayaka Watanabe
  • Patent number: 11986956
    Abstract: A joint according to one aspect of the disclosure includes: a joint body having an input gear meshing with a speed reduction mechanism, the joint body receiving an output shaft of a motor detachably coupled to the joint body; a motor flange disposed between the speed reduction mechanism and the motor and rotatably supporting the joint body; and an intermediate flange connecting between the motor flange and the motor. At least one fixing member for fixing the joint body and the output shaft to each other is provided at at least one position in the joint body that overlaps with the intermediate flange as viewed from a radial direction. The intermediate flange is formed as an annulus surrounding the joint body by a plurality of split pieces that can be split in a circumferential direction.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: May 21, 2024
    Assignee: NABTESCO CORPORATION
    Inventors: Koji Nakamura, Shinji Inoue
  • Patent number: 11983304
    Abstract: The present disclosure provides an on-board secure storage system capable of easily and quickly detecting unauthorized access to a storage device and a failure of the storage device, and appropriately using the detection result. the on-board secure storage system includes the storage device that has a controller, a non-volatile memory and an interface, and an electronic control unit that electronically controls a vehicle. After determining that unauthorized access or a failure occurs in the non-volatile memory, the controller performs predetermined processing according to the type of the unauthorized access or failure.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 14, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinji Inoue
  • Patent number: 11977501
    Abstract: The present disclosure provides an on-board storage system in which the time required for initializing a storage device is substantially shortened by devising a backend start timing. The on-board storage system includes: a storage device that has a controller, a NAND flash memory, and an interface; an electronic control unit that electronically controls a vehicle; and a sensor. The electronic control unit communicates with the storage device through the interface, the sensor transmits a detection result of the sensor to the electronic control unit, and the electronic control unit transmits a command to start initialization of the NAND flash memory to the controller when the transmitted detection result of the sensor indicates a driving-start preliminary operation.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 7, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinji Inoue
  • Publication number: 20240028674
    Abstract: A method is provided that determines authenticity of a second recording medium mounted in a second device by using a first device mounted with a first recording medium. A non-user area of the first recording medium previously records first identification information and first algorithm data. A controller of the first recording medium causes a first display device to display a first image pattern and, after display of the first image pattern, causes a first imaging device to capture a second image pattern displayed on a second display device of the second device. The controller decodes first code data from the second image pattern and utilizes the first algorithm data to perform arithmetic that uses the first identification information and a first variable value. The controller determines the second recording medium to be authentic if the decoded first code data matches an arithmetic result.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Inventors: Shinji INOUE, Yusuke SHIMIZU
  • Patent number: 11821507
    Abstract: The present disclosure relates to a manufacturing method of a speed reducer. The speed reducer includes an outer tube, a shaft portion, an input shaft, a first bearing, a speed reducing portion, and an attachment member. The shaft portion has a first receiving surface and a shaft end surface. The outer tube has a second receiving surface. The first bearing has a first inner ring and a first outer ring. The first receiving surface contacts the first inner ring. The second receiving surface contacts the first outer ring. A first machining accuracy is obtained based on a first parallelism between the first receiving surface and the shaft end surface. A second machining accuracy is obtained based on a second parallelism between the second receiving surface and the flange mounting surface. The manufacturing method includes performing machining such that the first machining accuracy becomes higher than the second machining accuracy.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: November 21, 2023
    Assignee: Nabtesco Corporation
    Inventors: Koji Nakamura, Shinji Inoue
  • Publication number: 20230341041
    Abstract: The present disclosure relates to a manufacturing method of a speed reducer. The speed reducer includes an outer tube, a shaft portion, an input shaft, a first bearing, a speed reducing portion, and an attachment member. The shaft portion has a first receiving surface and a shaft end surface. The outer tube has a second receiving surface. The first bearing has a first inner ring and a first outer ring. The first receiving surface contacts the first inner ring. The second receiving surface contacts the first outer ring. A first machining accuracy is obtained based on a first parallelism between the first receiving surface and the shaft end surface. A second machining accuracy is obtained based on a second parallelism between the second receiving surface and the flange mounting surface. The manufacturing method includes performing machining such that the first machining accuracy becomes higher than the second machining accuracy.
    Type: Application
    Filed: March 20, 2023
    Publication date: October 26, 2023
    Inventors: Koji NAKAMURA, Shinji INOUE
  • Publication number: 20230287972
    Abstract: A waterproof structure for a speed reducer according to one aspect of the disclosure includes: a speed reducer for decelerating a rotational driving force of an electric motor and transmitting the decelerated rotational driving force to a rotationally driven portion; a motor flange housing the speed reducer; a cover externally covering the speed reducer in a liquid-tight manner; and a holding plate and a first fixing bolt provided on an inner peripheral side of the cover to fix the cover to the motor flange.
    Type: Application
    Filed: February 27, 2023
    Publication date: September 14, 2023
    Inventors: Shinji INOUE, Ayaka WATANABE
  • Publication number: 20230249336
    Abstract: A joint according to one aspect of the disclosure includes: a joint body having an input gear meshing with a speed reduction mechanism, the joint body receiving an output shaft of a motor detachably coupled to the joint body; a motor flange disposed between the speed reduction mechanism and the motor and rotatably supporting the joint body; and an intermediate flange connecting between the motor flange and the motor. At least one fixing member for fixing the joint body and the output shaft to each other is provided at at least one position in the joint body that overlaps with the intermediate flange as viewed from a radial direction. The intermediate flange is formed as an annulus surrounding the joint body by a plurality of split pieces that can be split in a circumferential direction.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 10, 2023
    Inventors: Koji NAKAMURA, Shinji INOUE
  • Patent number: 11681051
    Abstract: The presence or absence of a preamble is detected with accuracy in a reception apparatus that receives a signal including a preamble. A reception section receives a subframe including a subframe preamble and a message and a frame including a frame preamble. A processing section performs a process of detecting the presence or absence of the subframe preamble according to whether or not a given relation holds between a reception timing of the subframe preamble and a reception timing of the frame preamble. A message decoding section extracts the message from the subframe and decodes the message in a case where the presence of the subframe preamble is detected.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 20, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazukuni Takanohashi, Tetsuhiro Futami, Katsuyuki Tanaka, Hideki Awata, Shinji Inoue, Tsunetomo Nakazato
  • Publication number: 20230068043
    Abstract: A semiconductor device capable of shortening an erasing time and suppressing deterioration of retention characteristics is provided. A semiconductor device includes: a semiconductor substrate having a main surface; a gate insulating film formed on the main surface; and a gate electrode formed on the gate insulating film. The gate insulating film includes a first silicon nitride film, and a first silicon oxide film arranged between the main surface and the first silicon nitride film and in contact with the first silicon nitride film. A Si—Si bond is formed in a boundary portion between the first silicon oxide film first silicon nitride film.
    Type: Application
    Filed: July 27, 2022
    Publication date: March 2, 2023
    Inventor: Shinji INOUE
  • Publication number: 20220138353
    Abstract: The present disclosure provides an on-board secure storage system capable of easily and quickly detecting unauthorized access to a storage device and a failure of the storage device, and appropriately using the detection result. the on-board secure storage system includes the storage device that has a controller, a non-volatile memory and an interface, and an electronic control unit that electronically controls a vehicle. After determining that unauthorized access or a failure occurs in the non-volatile memory, the controller performs predetermined processing according to the type of the unauthorized access or failure.
    Type: Application
    Filed: January 12, 2022
    Publication date: May 5, 2022
    Inventor: Shinji INOUE
  • Publication number: 20220138129
    Abstract: The present disclosure provides an on-board storage system in which the time required for initializing a storage device is substantially shortened by devising a backend start timing. The on-board storage system includes: a storage device that has a controller, a NAND flash memory, and an interface; an electronic control unit that electronically controls a vehicle; and a sensor. The electronic control unit communicates with the storage device through the interface, the sensor transmits a detection result of the sensor to the electronic control unit, and the electronic control unit transmits a command to start initialization of the NAND flash memory to the controller when the transmitted detection result of the sensor indicates a driving-start preliminary operation.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Inventor: Shinji INOUE
  • Publication number: 20220035046
    Abstract: The presence or absence of a preamble is detected with accuracy in a reception. apparatus that receives a signal including a preamble. A reception section receives a subframe including a subframe preamble and a message and a frame including a frame preamble. A processing section performs a process of detecting the presence or absence of the subframe preamble according to whether or not a given relation holds between a reception timing of the subframe preamble and a reception timing of the frame preamble. A message decoding section extracts the message from the subframe and decodes the message in a case where the presence of the subframe preamble is detected.
    Type: Application
    Filed: June 5, 2019
    Publication date: February 3, 2022
    Inventors: Kazukuni Takanohashi, Tetsuhiro Futami, Katsuyuki Tanaka, Hideki Awata, Shinji Inoue, Tsunetomo Nakazato
  • Publication number: 20210240396
    Abstract: A storage device is connected to a host device. The storage device includes a non-volatile memory, a logical area manager that divides the non-volatile memory into a plurality of logical areas, an area information storage that stores information regarding the plurality of logical areas, an access pattern manager that manages access patterns that are designated by the host device and each correspond to a corresponding one of the plurality of logical areas, an access pattern storage that stores information regarding the access patterns, an access pattern processing manager that selects, when any one of the plurality of logical areas is accessed from the host device, an access pattern corresponding to the any one of the plurality of logical areas accessed from the information, and an access processing management and execution unit that performs processing on the non-volatile memory based on the access pattern and transfers data to the host device.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Inventors: Shinji INOUE, Takuji MAEDA
  • Patent number: 10983929
    Abstract: In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 20, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinji Inoue
  • Publication number: 20200395913
    Abstract: There is provided a piezoelectric substrate including a lithium-containing metal compound crystal such as a lithium tantalate (LT) crystal, wherein potassium is contained in the substrate and the distribution of potassium is approximately uniform as observed in the direction of the thickness of the substrate. There is also provided a piezoelectric substrate, wherein a peak coming from Li—O lattice vibration and appearing around 380 cm?1 is shifted to a high wave number side compared with that in an untreated piezoelectric substrate having a conductivity of 1×10?15 S/cm or less in Raman spectra measured from the cross section direction.
    Type: Application
    Filed: June 29, 2018
    Publication date: December 17, 2020
    Inventors: Shuzo IWASHITA, Shinji INOUE, Hiroyuki YAMAJI, Hisao KONDOU