Patents by Inventor Shinji ITANO

Shinji ITANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for extracting IBIS simulation model
    Patent number: 8738347
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 27, 2014
    Inventors: Tadaaki Yoshimura, Yoji Nishio, Sadahiro Nonoyama, Koji Matsuo, Shinji Itano, Yoshiyuki Yagami
  • METHOD FOR EXTRACTING IBIS SIMULATION MODEL
    Publication number: 20120191437
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tadaaki YOSHIMURA, Yoji NISHIO, Sadahiro NONOYAMA, Koji MATSUO, Shinji ITANO, Yoshiyuki YAGAMI