Patents by Inventor Shinji Kadono
Shinji Kadono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8035979Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.Type: GrantFiled: December 13, 2010Date of Patent: October 11, 2011Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Publication number: 20110090657Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.Type: ApplicationFiled: December 13, 2010Publication date: April 21, 2011Applicants: CMK CORPORATION, RENESAS EASTERN JAPAN SEMICONDUCTOR INC.Inventors: Yutaka YOSHINO, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Patent number: 7894200Abstract: The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element.Type: GrantFiled: November 28, 2006Date of Patent: February 22, 2011Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Patent number: 5512847Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 6, 1994Date of Patent: April 30, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5495183Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: May 12, 1995Date of Patent: February 27, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Urragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5245224Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: March 3, 1992Date of Patent: September 14, 1993Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5103120Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: January 2, 1991Date of Patent: April 7, 1992Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5053644Abstract: A semiconductor integrated circuit is so designed that it is possible to form any one of the three different kinds of circuit configuration, that is, an inverter circuit, a Schmitt circuit and a common-mode circuit, as desired, by employing circuit elements prepared in advance and by changing wiring. Also disclosed is a semiconductor integrated circuit having these circuit configurations. The output stage of any one of the three kinds of circuit is constituted by a bipolar transistor, and the other portions are constituted by MOS field-effect transistors.Type: GrantFiled: May 16, 1986Date of Patent: October 1, 1991Assignee: Hitachi, Ltd.Inventors: Manabu Shibata, Akira Uragami, Shinji Kadono, Yukio Suzuki
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Patent number: 4983862Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 31, 1989Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4879480Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: September 2, 1988Date of Patent: November 7, 1989Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akiro Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4689503Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: January 31, 1984Date of Patent: August 25, 1987Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4678943Abstract: A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN.Type: GrantFiled: February 22, 1985Date of Patent: July 7, 1987Assignee: Hitachi, Ltd.Inventors: Akira Uragami, Yukio Suzuki, Shinji Kadono, Masahiro Iwamura, Ikuro Masuda, Tatsumi Yamauchi
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Patent number: 4158883Abstract: In a refresh control system including a main memory having a volatile memory, at least one processing unit for accessing the main memory, a memory bus for effecting signal transfer between the main memory and the processing unit and a supervision circuit for allotting use of the memory bus in response to a request signal, the refresh control system is characterized by a refresh control circuit for transferring the request signal to the supervision circuit at the time the refresh signal is required and for commanding the initiation of the refresh operation to the main memory in response to a grant signal from the supervision circuit.Type: GrantFiled: November 1, 1976Date of Patent: June 19, 1979Assignee: Hitachi, Ltd.Inventors: Shinji Kadono, Tsuneyo Chiba, Kiyoshi Umezawa