Abstract: Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor through a tightly coupled bus by the processors and a multiplexer coupled to the arbitration circuit, coupled to the processors through a local buses, and coupled to the co-processor through the local buses to transfer the commands received from the respective processors to the co-processor in accordance with a permission signal output by the arbitration circuit.

Abstract: A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a pipeline process for a subsequent instruction retrieved after the extended instruction is stopped at least for a period corresponding to a difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction.

Abstract: Disclosed is a multiprocessor apparatus including a co-processor provided in common to a plurality of processors and including a plurality of resources and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor by the processors through a co-processor bus, which is a tightly coupled bus, for each resource or each resource hierarchy according to instructions issued from the processors to the co-processor. Under control by the arbitration circuit, simultaneous use of a plurality of resources on a same hierarchy or different hierarchies in the co-processor by the processors through the tightly coupled bus is allowed.

Abstract: Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor through a tightly coupled bus by the processors.

Abstract: A boundary-scan device in which a plurality of signal paths are connected to the macro, each having a data signal input end and a data signal output end for signal transmission during normal mode operations. A plurality of circuits is provided for the plurality of signal paths, respectively. Each circuit is capable of capturing a signal transmission event that a signal has past through one of the plurality of signal paths during test mode operations.

Abstract: A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a pipeline process for a subsequent instruction retrieved after the extended instruction is stopped at least for a period corresponding to a difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction.

Abstract: A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (40), and a scan flip-flop (1). Control supply circuit (20) may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit (40) may provide a signal path that can apply control signal (Enable signal) to scan flip-flop (1) for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.

Abstract: A boundary-scan device to a macro is disclosed. A plurality of signal paths are connected to the macro, each having a data signal input end and a data signal output end for signal transmission during normal mode operations. A plurality of circuitries are provided for the plurality of signal paths, respectively. Each circuitry has capability of capturing a signal transmission event that a signal has past through one of the plurality of signal paths during test mode operations.

Abstract: A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (40), and a scan flip-flop (1). Control supply circuit (20) may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit (40) may provide a signal path that can apply control signal (Enable signal) to scan flip-flop (1) for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.