Abstract: A storage device for connection with a host device via an interface bus, includes a storage unit and a storage controller configured to control access to the storage unit and receive a power disable signal from the host device. The storage controller includes a plurality of processing units, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal.

Abstract: A storage device for connection with a host device via an interface bus, includes a storage unit and a storage controller configured to control access to the storage unit and receive a power disable signal from the host device. The storage controller includes a plurality of processing units, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal.

Abstract: A communication apparatus is configured to execute testing of whether or not the responding module is correctly responding to the plurality of commands transmitted and received between a transmission module and a reception module, the testing being performed via a loop-back mode transmission and reception path configured such that the reception module receives the command transmitted by the transmission module; and during the testing, following procedure is performed, which includes: transmitting the specific command by the transmission module; receiving the specific command by the reception module via the transmission and reception path; deactivating reception of the specific command; and transmitting a command different from the specific command subsequent to transmitting the specific command by the transmission module.

Abstract: A communication apparatus is configured to execute testing of whether or not the responding module is correctly responding to the plurality of commands transmitted and received between a transmission module and a reception module, the testing being performed via a loop-back mode transmission and reception path configured such that the reception module receives the command transmitted by the transmission module; and during the testing, following procedure is performed, which includes: transmitting the specific command by the transmission module; receiving the specific command by the reception module via the transmission and reception path; deactivating reception of the specific command; and transmitting a command different from the specific command subsequent to transmitting the specific command by the transmission module.

Abstract: A communication apparatus is configured to execute testing of whether or not the responding module is correctly responding to the plurality of commands transmitted and received between a transmission module and a reception module, the testing being performed via a loop-back mode transmission and reception path configured such that the reception module receives the command transmitted by the transmission module; and during the testing, following procedure is performed, which includes: transmitting the specific command by the transmission module; receiving the specific command by the reception module via the transmission and reception path; deactivating reception of the specific command; and transmitting a command different from the specific command subsequent to transmitting the specific command by the transmission module.

Abstract: According to one embodiment, a serial ATA interface apparatus having an S-ATA bridge. The S-ATA bridge is to be connected to a host system by a serial ATA bus. The S-ATA bridge has a shadow register and a buffer memory. The shadow register stores commands. The buffer memory can access a HDC. The S-ATA bridge finishes processing the commands before it outputs a response signal to the host system.

Abstract: A PCI-ISA bridge device includes a PCI interface for driving a target ready signal line when PCI-ISA bridge device is address-specified as a current target by a read cycle on a PCI bus, and a status register for setting status information indicating respective states of a plurality of DMA request signals inputted to DMA controller. Further the PCI interface circuit includes a wait control circuit for inserting a predetermined wait time period in the timing for driving the target ready signal line, when the transaction is a read cycle for reading the content of the status register.