Patents by Inventor Shinji Miyagaki
Shinji Miyagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7741684Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: GrantFiled: July 19, 2005Date of Patent: June 22, 2010Assignee: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Publication number: 20050247988Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: ApplicationFiled: July 19, 2005Publication date: November 10, 2005Applicant: FUJITSU LIMITEDInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Patent number: 6946351Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1?xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: GrantFiled: February 2, 2004Date of Patent: September 20, 2005Assignee: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Publication number: 20040238841Abstract: The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7<x<1) formed over a semiconductor substrate, and a second dielectric film different from the first dielectric film formed over the first dielectric film; and a gate electrode formed over the gate insulating film and including a polycrystalline silicon film, whereby the local abnormal growth of the polycrystalline silicon film in the process of forming the polycrystalline silicon film is prevented, and the gate leakage current can be much decreased.Type: ApplicationFiled: February 2, 2004Publication date: December 2, 2004Applicant: Fujitsu LimitedInventors: Chikako Yoshida, Hiroshi Minakata, Masaomi Yamaguchi, Shinji Miyagaki, Yasuyuki Tamura
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Publication number: 20030222316Abstract: The semiconductor device comprises a p type silicon substrate 18, a gate insulation film 27 of a layer film of a silicon oxynitride film 25 and an aluminum oxide film 26 which are sequentially formed on the p type silicon substrate 18, and a gate electrode 28 formed on the gate insulation film 27. Accordingly, both the flat band voltage shift and the hysteresis can be depressed. Thus, MIS transistors having good device characteristics can be realized.Type: ApplicationFiled: March 7, 2003Publication date: December 4, 2003Applicant: FUJITSU LIMITEDInventors: Shinji Miyagaki, Masaomi Yamaguchi, Yasuyuki Tamura, Yoshiaki Tanida, Chikako Yoshida, Yoshihiro Sugiyama, Hitoshi Tanaka
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Patent number: 6188090Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: February 20, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 5834362Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: March 21, 1996Date of Patent: November 10, 1998Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 5492860Abstract: A method of growing a layer of a III-V compound semiconductor on a silicon substrate comprises an oxide layer removing step of removing an oxide layer on a surface of the silicon substrate at a first temperature, a low-temperature grown layer forming step of forming a low-temperature grown layer of the III-V compound semiconductor on the silicon substrate while introducing a source gas for Group III and a source gas for Group V at a second temperature lower than the first temperature, and a single crystal layer growing step of growing a single crystal layer of the Group III-V compound semiconductor on the low-temperature grown layer while introducing the source gas for Group III and the source gas for Group V at a third temperature higher than the second temperature and lower than the first temperature.Type: GrantFiled: April 16, 1993Date of Patent: February 20, 1996Assignee: Fujitsu LimitedInventors: Satoshi Ohkubo, Shinji Miyagaki
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Patent number: 5094978Abstract: A method of forming a pattern of a transparent conducting film such as an indium tin oxide film, formed on the surface of a substrate including Si and being heated. A two-step etching method is employed, in which the transparent conducting film is wet-etched by an aqueous solution of a halogenide and thereafter an interfacial reacted layer generated at the interface of the transparent conducting film and substrate including Si is etched by a plasma etching method using a halogen.Type: GrantFiled: July 19, 1990Date of Patent: March 10, 1992Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Seigen Ri
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Patent number: 5093564Abstract: A photosensor comprises an insulator layer, a first electrode on the insulator layer for collecting first type carriers formed upon incidence of optical radiation, the first electrode being segmented into a plurality of pixel electrodes separated from each other by a gap, a first silicon carbide layer provided on the insulator layer to cover the plurality of pixel electrodes including the gap separating adjacent pixel electrodes, an optical absorption layer of amorphous silicon provided on the silicon carbide layer continuously such that the amorphous silicon layer extends over the plurality of pixel electrodes and the gap between adjacent pixel electrodes, the optical absorption layer producing the first type carriers and second type carriers having opposing polarity to the first type carriers upon incidence of the optical radiation, a second silicon carbide layer provided on the amorphous silicon layer for protecting the optical absorption layer from chemical reaction, and a second electrode of a transparenType: GrantFiled: November 8, 1990Date of Patent: March 3, 1992Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Seigen Ri
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Patent number: 5066612Abstract: In the course of a production of a semiconductor device with a multilayer insulating layer, when a contact hole is opened in the multilayer insulating layer, an insulating layer activating a metal selective vapor-growth appears at the side wall of the contact hole. A thin metal (e.g., tungsten) layer is selectively deposited in the contact hole. In another case, another metal layer appears within the contact hole. An insulating film preventing a metal selective vapor-growth is deposited over the whole surface of the side wall of the contact hole, the metal layer and a top surface of the multilayer insulating layer, and is anisotropically etched to leave a portion of the film lying on the side wall only as a side wall insulating film. The contact hole is completely filled with another metal (tungsten) by a selective vapor-growth method, to flatten an exposed surface, and then a conductor (e.g.Type: GrantFiled: January 3, 1991Date of Patent: November 19, 1991Assignee: Fujitsu LimitedInventors: Takayuki Ohba, Shinji Miyagaki, Tatsushi Hara, Kenji Morishita, Seiichi Suzuki, Seigen Ri