Abstract: A data-processing apparatus provided with a bit boundary block transfer unit. A CPU forms a list of parameters required for transferring characters forming one block of text, and stores the list in a memory. A parameter control section of the boundary block transfer unit sequentially reads the parameters, and writes them in a parameter file. Meanwhile, the CPU processes the data. When the block of text has been transferred, an interrupt is supplied to the CPU. The CPU can form a list of only those parameters which must be changed for characters of the same type. These parameters are rewritten as the characters are transferred, one by one. In another data-processing apparatus of the invention, a CPU loads a register with data showing the type of characters to be transferred. It can input a variable parameter to a memory storing fixed parameters.

Abstract: According to this invention, an LSI circuit is provided with a pseudorandom data generating circuit for producing pseudorandom data and a timing signal generating circuit for producing test timing signals in synchronism with a control input timing signal necessary for the operation of an internal logic circuit. The LSI circuit has two input lines, a control input line and a data input line. The LSI circuit further includes a circuit, which selectively supplies the timing signals from the timing signal generating circuit on the control input line and selectively supplies the pseudorandom data from the psuedorandom data generating circuit on the data input line. Consequently, the LSI circuit automatically generates control input signals and data input signals within itself to carry out the self-checking operation.

Abstract: In a read-out control system for a control storage device having a selector switch to select address information, a control storage means which responds to address information applied from the selector switch through a driver to produce a microinstruction from an address specified by the address information, a microinstruction register for holding a microinstruction read out from the control storage device, and an address register with a count function to increment the address information from the selector switch, the address register with a count function stores the address information currently stored in the control storage device at either the leading or trailing edge of a first supplementary clock signal produced in the machine cycle, and counts up the address information stored by +1 in synchronism with a second supplementary clock signal which rises or falls at the leading edge or the trailing edge of the machine clock signal representing the start of the next machine cycle.

Abstract: A microprogram-controlled data processor executes a user instruction having an operation code field to specify the type of user instruction and at least one operand field to designate one of the general registers provided in a register file. The data processor comprises a logic circuit including the register file and at least one register connected directly to the register file for storing address data for addressing the register file. The data in the operand field of the user instruction is stored in the register during a microstep immediately before the first microstep of the microprogram for executing the user instruction. The output signal of the register designates one of the general registers provided in the register file.