Abstract: An ON-state voltage is reduced. A line of gate trenches 8 is formed on an n-type silicon layer (a SOI layer) 3 so as to divide a p-type base layer 4 and an n-type emitter layer 5. The gate trench 8 extends from the n-type emitter layer 5 toward a collector electrode 21. A gate electrode 10 is buried in the gate trench 8 with a gate insulation film 9 interposed therebetween. The gate electrode 10 is provided opposite to a vertical section of the p-type base layer 4. Therefore, a channel width can be kept great. Furthermore, a wide region of the n-type silicon layer 3 which is provided opposite to the gate trench 8 functions as an accumulation layer of a hole. As a result, the ON-state voltage can be reduced.