Patents by Inventor Shinji Nunotani

Shinji Nunotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887858
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 30, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Nunotani, Shinji Onzuka
  • Publication number: 20230253233
    Abstract: A semiconductor manufacturing apparatus includes first and second stages and a peripheral edge holder. The first stage supports a wafer with a resin sheet interposed. The wafer is separated into a central part and a peripheral edge part on the resin sheet. The first stage supports the central part of the wafer. The second stage surrounds the first stage and fixes an outer circumference part of the resin sheet. The outer circumference part is positioned outward of the first stage. The second stage is movable relative to the first stage to apply tension to the outer circumference part of the resin sheet. The peripheral edge holder holds the peripheral edge part of the wafer. The first and second stages move relative to each other so that the tension peels the resin sheet from the peripheral edge part of the wafer fixed to the peripheral edge holder.
    Type: Application
    Filed: September 2, 2022
    Publication date: August 10, 2023
    Inventors: Shinji NUNOTANI, Kazuo FUJIMURA
  • Patent number: 11694900
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 4, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Publication number: 20220246734
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji NUNOTANI, Shinji ONZUKA
  • Patent number: 11342426
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Nunotani, Shinji Onzuka
  • Publication number: 20220020592
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Toshiyuki NISHIKAWA, Kazuhiko KOMATSU, Shinji NUNOTANI, Yoshiyuki HARADA, Hideto SUGAWARA
  • Patent number: 11158514
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Publication number: 20210066130
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 4, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji NUNOTANI, Shinji ONZUKA
  • Publication number: 20200303197
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 24, 2020
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Patent number: 9887328
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideko Mukaida, Mitsuyoshi Endo, Hideto Furuyama, Yoshiaki Sugizaki, Kazuo Fujimura, Shinya Ito, Shinji Nunotani
  • Patent number: 9472713
    Abstract: An embodiment has an emission layer, a first electrode having a reflective metal layer, an insulating layer, first and second conductivity type layers, and a second electrode. The insulating layer is provided on the first electrode and has an opening where a portion of the first electrode is provided. The first conductivity type layer is provided between the insulating layer and the emission layer and has bandgap energy larger than that of the emission layer. The second conductivity type layer is provided on the emission layer and has a current diffusion layer and a second contact layer. The second contact layer is not superimposed on the opening of the insulating layer, and a thickness of the current diffusion layer is larger than that of the first contact layer. The second electrode has a pad portion and a thin portion extends from the pad portion onto the second contact layer.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Genei, Tokuhiko Matsunaga, Katsufumi Kondo, Shinji Nunotani
  • Patent number: 9444012
    Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, and a second electrode layer. The structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer includes a metal portion, plural first opening portions, and at least one second opening portion. The metal portion has a thickness of not less than 10 nanometers and not more than 200 nanometers along a direction from the first semiconductor layer toward the second semiconductor layer. The plural first opening portions each have a circle equivalent diameter of not less than 10 nanometers and not more than 1 micrometer. The at least one second opening portion has a circle equivalent diameter of more than 1 micrometer and not more than 30 micrometers.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Akira Fujimoto, Ryota Kitagawa, Takanobu Kamakura, Shinji Nunotani, Eishi Tsutsumi, Masaaki Ogawa
  • Patent number: 9444017
    Abstract: According to one embodiment, the second insulating film is provided between the first interconnect portion and the second interconnect portion, and at an outer periphery of a side face of the semiconductor layer. The optical layer is provided on the first side, and on the second insulating film at the outer periphery. The optical layer is transmissive with respect to light emitted from the light emitting layer. The film is provided between the second insulating film at the outer periphery and the optical layer. The film has a roughened surface on a side in contact with the optical layer.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Nunotani, Kazuo Fujimura, Shinya Ito
  • Patent number: 9437779
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Asakawa, Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9331248
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 3, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumi Masunaga, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Patent number: 9318664
    Abstract: According to one embodiment, a semiconductor light emitting element includes: a support substrate; a bonding layer provided on the support substrate; an LED layer provided on the bonding layer; and a buffer layer softer than the bonding layer. The buffer layer is placed in one of between the support substrate and the bonding layer and between the bonding layer and the LED layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Nunotani, Yasuhiko Akaike, Yoshinori Natsume, Kazuyoshi Furukawa
  • Patent number: 9318661
    Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a first electrode layer, a light emitting layer, a second semiconductor layer, a third semiconductor layer and a second electrode layer. The first electrode layer includes a metal portion having a plurality of opening portions. The opening portions penetrate the metal portion and have an equivalent circle diameter of a shape of the opening portions. The light emitting layer is between the first semiconductor layer and the first electrode layer. The second semiconductor layer of a second conductivity type is between the light emitting layer and the first electrode layer. The third semiconductor layer of a second conductivity type is between the second semiconductor layer and the first electrode layer. The second electrode layer is connected to the first semiconductor layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Eishi Tsutsumi, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20160079497
    Abstract: A semiconductor light emitting device is provided. The semiconductor light emitting device includes a semiconductor substrate having a first face on a first side, a second face on a second side opposite to the first face, and a third face which joins the first face and the second face. The semiconductor light emitting device further includes a first light reflection film in contact with at least a portion of the third face of the semiconductor substrate. The semiconductor device further includes a laminated body that is provided on the second side of the semiconductor substrate, and includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: March 1, 2015
    Publication date: March 17, 2016
    Inventors: Rintaro OKAMOTO, Shinji NUNOTANI
  • Patent number: 9224919
    Abstract: According to one embodiment, the second insulating film is provided between the first interconnect portion and the second interconnect portion, and at an outer periphery of a side face of the semiconductor layer. The optical layer is provided on the first side and on the second insulating film at the outer periphery. The optical layer is transmissive with respect to light emitted from the light emitting layer. A plurality of protrusions and a plurality of recesses are provided at the first side. Peaks of the protrusions are positioned closer to the second side than an end on the second insulating film side of the optical layer at the outer periphery.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Fujimura, Hironori Yamasaki, Tadashi Ono, Shinsaku Kubo, Shinji Nunotani
  • Publication number: 20150311393
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.
    Type: Application
    Filed: June 17, 2015
    Publication date: October 29, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji ASAKAWA, Akira FUJIMOTO, Ryota KITAGAWA, Kumi MASUNAGA, Takanobu KAMAKURA, Shinji NUNOTANI