Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: The nonvolatile semiconductor memory device has a floating gate electrode that is formed on the semiconductor region and stores carriers injected from the semiconductor region and a control gate electrode that controls the quantity of stored carriers by applying a predetermined voltage to the floating gate electrode. The source region is formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode, while the drain region is formed on the other of the side regions thereof. The drain region creates an electric field from which the carriers injected into the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.