Abstract: A semiconductor memory device according to the present invention is mounted on a memory module. The semiconductor memory device has a redundant circuit and a chip select circuit. The semiconductor memory device is allowed to be selected in the memory module by using a memory address that has been replaced with a redundant circuit as identifier information specific to the semiconductor memory device. The semiconductor memory device having the identifier information that coincides with a memory address inputted in a state of the memory module is selected and brought into an operation mode or a standby mode.

Abstract: A semiconductor memory device according to the present invention is mounted on a memory module. The semiconductor memory device has a redundant circuit and a chip select circuit. The semiconductor memory device is allowed to be selected in the memory module by using a memory address that has been replaced with a redundant circuit as identifier information specific to the semiconductor memory device. The semiconductor memory device having the identifier information that coincides with a memory address inputted in a state of the memory module is selected and brought into an operation mode or a standby mode.

Abstract: A memory module includes a first group of integrated-circuit memory units each having a control pin terminal, and a second group of integrated-circuit memory units. Each memory unit of the second group includes a control pin terminal and at least one memory unit of the second group further includes at least one vacant pin terminal. First connections are provided for receiving a control signal from an external source and supplying it to the control pin terminal of each of the first group of memory units. Second connections are provided for receiving and supplying the control signal to the control pin terminal of each of the second group of memory units and to at least one vacant pin terminal of the second group of memory units. Preferably, the vacant pin terminal is connected to a circuit equivalent in operating characteristics to a circuit connected to the control pin terminal.

Abstract: A controlled delay circuit for use in a synchronized semiconductor memory, comprises a reference delay, a delay circuit for controlling an internal circuit, and a comparing and adjusting circuitry comparing a delay amount of the reference delay with a cycle of an external synchronous signal, at a mode register setting time, for automatically adjusting a delay time of the delay circuit on the basis of the result of the comparison.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in column and row directions in a matrix manner, and an oscillating section for oscillating in response to a self-refresh operation mode to generate an oscillation signal. A timer signal generating section outputs, as a timer signal based on the oscillation signal from the oscillating section, a first clock signal in a normal operation mode and a second clock signal in a test operation mode, the second clock signal being longer than the first clock signal and associated with a maximum usable temperature of the semiconductor memory device.