Patents by Inventor Shinji Tada
Shinji Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187323Abstract: A semiconductor device, including a case that has a first power terminal including a first bonding area and a second power terminal including a second bonding area, and an insulating unit located between the first power terminal and the second power terminal, and having a shape of a flat plate, the insulating unit being bonded to the case. The insulating unit has a first insulating portion in a sheet form, and a second insulating portion which covers an upper surface, a lower surface, or both the upper and lower surfaces, of the first insulating portion. The first bonding area and the second bonding area are exposed from the insulating unit and from the case.Type: ApplicationFiled: October 27, 2022Publication date: June 15, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shinji TADA, Yuma MURATA
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Patent number: 11664342Abstract: A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more.Type: GrantFiled: June 11, 2021Date of Patent: May 30, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinji Tada, Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
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Publication number: 20230120152Abstract: A semiconductor module includes a first case having a first side face, a first insulating paper disposed on the first case and having a first width in a first direction and having a notch with a second width smaller than the first width, a first terminal between the first case and the first insulating paper, having an exposed portion exposed from the first insulating paper at an area where the notch is formed, and a second terminal on the first insulating paper at a side opposite to a side where the first terminal is disposed. The first terminal and the first insulating paper have extended portions extending to an outside of the first case from the first side face so that a portion of the first insulating paper where the notch is formed and the exposed portion of the first terminal are located at the outside of the first case.Type: ApplicationFiled: August 26, 2022Publication date: April 20, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yuma MURATA, Ryoichi KATO, Shinji TADA
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Publication number: 20210407955Abstract: A semiconductor device, including a capacitor, a semiconductor module having a first power terminal formed on a front surface of a first insulating member, and a connecting member electrically connecting and mechanically coupling the semiconductor module and the capacitor to each other, the connecting member having a front surface and a rear surface opposite to each other, the rear surface being on a front surface of the first power terminal. The connecting member is bonded to the semiconductor module via a first welded portion, which penetrates the front and rear surfaces of the connecting member, and penetrates the front surface of the first power terminal, in a thickness direction of the semiconductor device, a distance in the thickness direction between a bottommost portion of first welded portion and the front surface of the first insulating member being 0.3 mm or more.Type: ApplicationFiled: June 11, 2021Publication date: December 30, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shinji TADA, Ryoichi KATO, Yoshinari IKEDA, Yuma MURATA
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Patent number: 10446460Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.Type: GrantFiled: March 7, 2018Date of Patent: October 15, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
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Patent number: 10157877Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.Type: GrantFiled: October 8, 2015Date of Patent: December 18, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazumasa Kido, Takashi Saitou, Kyouhei Fukuda, Shinji Tada, Fumihiko Momose, Yoshitaka Nishimura
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Publication number: 20180315676Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.Type: ApplicationFiled: March 7, 2018Publication date: November 1, 2018Applicant: Fuji Electric Co., Ltd.Inventors: Hiromichi GOHARA, Kohei YAMAUCHI, Shinji TADA, Tatsuo NISHIZAWA, Yoshitaka NISHIMURA
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Patent number: 9786587Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: GrantFiled: July 8, 2016Date of Patent: October 10, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tatsuo Nishizawa, Shinji Tada, Yoshito Kinoshita, Yoshinari Ikeda, Eiji Mochizuki
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Patent number: 9579746Abstract: A thermocompression bonding structure includes a first member and a second member having a linear expansion coefficient different from that of the first member; and metal fine particles interposed between the first and second members as a bonding material to thermocompression bond the two members. The two members are disposed to apply thermal stress generating between the first member and the second member as pressurizing force on a bonding surface between the two members, and to increase temperature to thermocompression bond the first member and the second member.Type: GrantFiled: March 25, 2014Date of Patent: February 28, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshito Kinoshita, Eiji Mochizuki, Tatsuo Nishizawa, Shinji Tada
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Patent number: 9504154Abstract: A semiconductor device composed of a plurality of semiconductor modules exhibiting a large current carrying capacity for a semiconductor device as a whole is disclosed. The connection between the plurality of semiconductor modules is conducted by means of optimum construction suited to the semiconductor device. The device comprises a semiconductor module having externally connecting terminals protruding out of a casing, bus bars electrically connecting the specific externally connecting terminals of the plurality of semiconductor modules arranged in parallel with each other, and a semiconductor module case covering and fastening the plurality of semiconductor modules connected with the bus bars. The bus bars and the externally connecting terminals of the semiconductor modules are joined by means of laser welding.Type: GrantFiled: May 28, 2014Date of Patent: November 22, 2016Assignee: Fuji Electric Co., Ltd.Inventors: Shinji Tada, Eiji Mochizuki, Hideyo Nakamura, Masafumi Horio
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Publication number: 20160322287Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Tatsuo NISHIZAWA, Shinji TADA, Yoshito KINOSHITA, Yoshinari IKEDA, Eiji MOCHIZUKI
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Patent number: 9406603Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: GrantFiled: May 12, 2014Date of Patent: August 2, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tatsuo Nishizawa, Shinji Tada, Yoshito Kinoshita, Yoshinari Ikeda, Eiji Mochizuki
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Publication number: 20160035690Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.Type: ApplicationFiled: October 8, 2015Publication date: February 4, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazumasa KIDO, Takashi SAITOU, Kyouhei FUKUDA, Shinji TADA, Fumihiko MOMOSE, Yoshitaka NISHIMURA
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Publication number: 20140355219Abstract: A semiconductor device composed of a plurality of semiconductor modules exhibiting a large current carrying capacity for a semiconductor device as a whole is disclosed. The connection between the plurality of semiconductor modules is conducted by means of optimum construction suited to the semiconductor device. The device comprises a semiconductor module having externally connecting terminals protruding out of a casing, bus bars electrically connecting the specific externally connecting terminals of the plurality of semiconductor modules arranged in parallel with each other, and a semiconductor module case covering and fastening the plurality of semiconductor modules connected with the bus bars. The bus bars and the externally connecting terminals of the semiconductor modules are joined by means of laser welding.Type: ApplicationFiled: May 28, 2014Publication date: December 4, 2014Applicant: Fuji Electric Co., Ltd.Inventors: Shinji TADA, Eiji MOCHIZUKI, Hideyo NAKAMURA, Masafumi HORIO
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Publication number: 20140301769Abstract: A thermocompression bonding structure includes a first member and a second member having a linear expansion coefficient different from that of the first member; and metal fine particles interposed between the first and second members as a bonding material to thermocompression bond the two members. The two members are disposed to apply thermal stress generating between the first member and the second member as pressurizing force on a bonding surface between the two members, and to increase temperature to thermocompression bond the first member and the second member.Type: ApplicationFiled: March 25, 2014Publication date: October 9, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshito KINOSHITA, Eiji MOCHIZUKI, Tatsuo NISHIZAWA, Shinji TADA
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Publication number: 20140246783Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Tatsuo NISHIZAWA, Shinji TADA, Yoshito KINOSHITA, Yoshinari IKEDA, Eiji MOCHIZUKI
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Patent number: 8196300Abstract: A manufacturing method of an electric contact and manufacturing equipment of the electric contact. A contact and a metal base are superimposed and support by a jig, and a rotational tool, which rotates at a predetermined speed and advances/retracts to/from the jig, is pressed into a surface, which is not contacted with the contact, of the metal base while being rotated, so that the contact and the metal base are joined by solid state diffusion welding by using frictional heat generated by friction between the rotational tool and the metal base, and then the rotational tool is retracted from the metal base.Type: GrantFiled: January 16, 2009Date of Patent: June 12, 2012Assignee: Fuji Electric Fa Components & Systems, Ltd.Inventors: Seiji Imamura, Shinji Tada, Mamoru Akimoto, Yuuichi Yamamoto, Toshiya Shibayanagi
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Publication number: 20110099808Abstract: A manufacturing method of an electric contact and manufacturing equipment of the electric contact. A contact and a metal base are superimposed and support by a jig, and a rotational tool, which rotates at a predetermined speed and advances/retracts to/from the jig, is pressed into a surface, which is not contacted with the contact, of the metal base while being rotated, so that the contact and the metal base are joined by solid state diffusion welding by using frictional heat generated by friction between the rotational tool and the metal base, and then the rotational tool is retracted from the metal base.Type: ApplicationFiled: January 16, 2009Publication date: May 5, 2011Inventors: Seiji Imamura, Shinji Tada, Mamoru Akimoto, Yuuichi Yamamoto, Toshiya Shibayanagi
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Patent number: 6425173Abstract: A forming die including of a holder having an upper portion and a lower portion, each portion having a main substrate extending in a first longitudinal direction. A fixing substrate is located on one end of the main substrate and a movable substrate is located on an opposite end of the main substrate and is movable along the main substrate in the first longitudinal direction. A plurality of die forming segments are situated between the movable substrate and the fixing substrate. Tie rods extend along the main substrate outside the periphery of the plurality of die forming segments, and connect the movable substrate and the fixing substrate to one another.Type: GrantFiled: August 29, 2000Date of Patent: July 30, 2002Assignee: NGK Insulators, Ltd.Inventors: Akio Enomoto, Shinji Tada, Hiroshi Kashiwagi
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Patent number: 6365097Abstract: A novel lead-free Sn—Bi based alloy having an improved wettability in comparison to conventional Sn—Bi based alloys, a melting point lower than 221° C., the eutectic point of an Sn—Ag alloy, and proper bonding and heat-resistant properties is provided. This alloy is an Sn—Bi based alloy containing tin as a major component, and 21 wt.% or less bismuth, 4 wt.% or less silver, 2 wt.% or less copper (inclusive of zero), and 0.2 wt.% or less nickel.Type: GrantFiled: January 27, 2000Date of Patent: April 2, 2002Assignee: Fuji Electric Co., Ltd.Inventors: Mitsuo Yamashita, Shinji Tada, Kunio Shiokawa