Patents by Inventor Shinji Takashima

Shinji Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11599192
    Abstract: Provided is an image presentation apparatus configured to present a virtual space image to a user. The image presentation apparatus receives acquisition information that is acquired during the presentation of the image and a notification from the user that indicates that the user has entered a predetermined condition. The image presentation apparatus learns a relationship between the acquisition information and content of the notification by machine learning. A result of the machine learning is used for predetermined processing during the presentation of the virtual space image to the user.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 7, 2023
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventor: Shinji Takashima
  • Publication number: 20210116997
    Abstract: Provided is an image presentation apparatus configured to present a virtual space image to a user. The image presentation apparatus receives acquisition information that is acquired during the presentation of the image and a notification from the user that indicates that the user has entered a predetermined condition. The image presentation apparatus learns a relationship between the acquisition information and content of the notification by machine learning. A result of the machine learning is used for predetermined processing during the presentation of the virtual space image to the user.
    Type: Application
    Filed: April 26, 2018
    Publication date: April 22, 2021
    Inventor: Shinji TAKASHIMA
  • Patent number: 9465727
    Abstract: A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory chips electrically connected with one another by a bus (e.g. address bus, data bus, control bus, etc.), which are disposed in a stacked arrangement and extend through the plurality of memory chips in a stacking direction, and a memory controller connected to a plurality of processors and to the bus, and further to a chip select signal line for outputting a chip select signal to each of the plurality of memory chips. The memory controller converts an address signal from each of the processors into a set of the chip select signal and the address signal, which is outputted to the address bus, so as to relay inputs and outputs of data between each of the processors and each of the memory chips.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: October 11, 2016
    Assignees: Sony Corporation, Sony Interactive Entertainment Inc.
    Inventor: Shinji Takashima
  • Publication number: 20160109957
    Abstract: A recording unit records an event list in which time information and physical solid image information are associated with an event. An image processing portion determines whether an image corresponding to physical solid image information recorded in the recording unit is included in a picked up image picked up within a time zone specified by the time information recorded in the recording unit. A condition determination portion determines that an event starting condition is satisfied if it is determined that the image corresponding to the physical solid image information is included in the picked up image. A starting instruction portion instructs an application execution section to execute processing of the application. The application execution section starts processing of the application associated with the event whose starting condition is satisfied.
    Type: Application
    Filed: May 9, 2013
    Publication date: April 21, 2016
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Shinji Takashima
  • Patent number: 8996893
    Abstract: Provided is a power supply circuit capable of suppressing a power supply voltage to be input to an integrated circuit device to low level. A power supply circuit (10) controls power supply to an integrated circuit device (30) having a built-in IC chip (31). The power supply circuit (10) acquires a value of a current flowing in the integrated circuit device, and changes a power supply voltage to be input to the integrated circuit device (30), in accordance with the acquired value of the current.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 31, 2015
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Tsuyoshi Ohashi, Shinji Takashima
  • Patent number: 8975951
    Abstract: Electronic apparatus that can suppress the operating voltage of an incorporated semiconductor integrated circuit to a low voltage is provided. Electronic apparatus 1 includes a power supply circuit 13, a semiconductor integrated circuit 10 that operates by a supply voltage supplied from the power supply circuit 13, and a temperature sensor 11 that measures the temperature of the semiconductor integrated circuit 10. The power supply circuit 13 decreases the supply voltage according to a rise in the measured temperature.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 10, 2015
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Takeshi Inoue, Shinji Takashima
  • Publication number: 20140022003
    Abstract: Electronic apparatus that can suppress the operating voltage of an incorporated semiconductor integrated circuit to a low voltage is provided. Electronic apparatus 1 includes a power supply circuit 13, a semiconductor integrated circuit 10 that operates by a supply voltage supplied from the power supply circuit 13, and a temperature sensor 11 that measures the temperature of the semiconductor integrated circuit 10. The power supply circuit 13 decreases the supply voltage according to a rise in the measured temperature.
    Type: Application
    Filed: April 10, 2012
    Publication date: January 23, 2014
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Takeshi Inoue, Shinji Takashima
  • Publication number: 20130262786
    Abstract: A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory chips electrically connected with one another by a bus (e.g. address bus, data bus, control bus, etc.), which are disposed in a stacked arrangement and extend through the plurality of memory chips in a stacking direction, and a memory controller connected to a plurality of processors and to the bus, and further to a chip select signal line for outputting a chip select signal to each of the plurality of memory chips. The memory controller converts an address signal from each of the processors into a set of the chip select signal and the address signal, which is outputted to the address bus, so as to relay inputs and outputs of data between each of the processors and each of the memory chips.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 3, 2013
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Shinji TAKASHIMA
  • Publication number: 20120110355
    Abstract: Provided is a power supply circuit capable of suppressing a power supply voltage to be input to an integrated circuit device to low level. A power supply circuit (10) controls power supply to an integrated circuit device (30) having a built-in IC chip (31). The power supply circuit (10) acquires a value of a current flowing in the integrated circuit device, and changes a power supply voltage to be input to the integrated circuit device (30), in accordance with the acquired value of the current.
    Type: Application
    Filed: June 7, 2010
    Publication date: May 3, 2012
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Tsuyoshi Ohashi, Shinji Takashima
  • Patent number: 6880061
    Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: April 12, 2005
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Shinji Takashima
  • Publication number: 20020162054
    Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 31, 2002
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Shinji Takashima
  • Patent number: 5440680
    Abstract: An image display controller includes a first memory for storing data of an image to be displayed in a first window; a second memory for storing data of an image to be displayed in a second window, where no data is read from the second memory for image display during the data reading operation in the first memory; and a third memory for storing data of an overlay image on which the image of the first or second memory is superimposed, and also storing window data to set the range of the windows. The controller is arranged to prevent any disordered display of images and is capable of displaying an increased number of windows.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: August 8, 1995
    Assignee: Sony Corporation
    Inventors: Norihito Ichikawa, Masatoshi Imai, Hidehiro Hirase, Shinji Takashima
  • Patent number: D396829
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: August 11, 1998
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Shinji Takashima, Toshihiko Shimizu