Patents by Inventor Shinji Tojo

Shinji Tojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7470568
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 30, 2008
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20080032453
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 7, 2008
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 7262083
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: August 28, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20040142512
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 6699737
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: March 2, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20030068842
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: September 13, 2002
    Publication date: April 10, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 5920115
    Abstract: To provide a semiconductor device in which a thin resin film is provided on the whole margin of the principal plane of a semiconductor chip a lead is provided on the thin resin film, the lead is electrically connected with input and output electrode pads of the semiconductor chip, and the electrical joint is covered and sealed with a seal resin.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: July 6, 1999
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Corp.
    Inventors: Makoto Kimura, Shinji Tojo, Takahiro Fujioka, Akihiko Narisawa, Yoshiyuki Tanigawa, Shinya Kanamitsu, Koji Akimoto, Hiroyuki Mouri
  • Patent number: 5767571
    Abstract: To provide a semiconductor device in which a thin resin film is provided on the whole margin of the principal plane of a semiconductor chip, a lead is provided on the thin resin film, the lead is electrically connected with input and output electrode pads of the semiconductor chip, and the electrical joint is covered and sealed with a seal resin.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: June 16, 1998
    Assignees: Hitachi, Ltd, Hitachi Device Engineering Corp
    Inventors: Makoto Kimura, Shinji Tojo, Takahiro Fujioka, Akihiko Narisawa, Yoshiyuki Tanigawa, Shinya Kanamitsu, Koji Akimoto, Hiroyuki Mouri