Abstract: A liquid crystal display device (1) includes a liquid crystal display panel (2), a metal backlight chassis (4), a metal bezel (13), a printed circuit board (31), an electric conductor (14) via which the metal backlight chassis (4) and a ground land part (31f) of the printed circuit board (31) are electrically connected with each other, and a frame (10) having an insertion hole in which the electric conductor (14) is inserted.

Abstract: A liquid crystal display device (1) includes a liquid crystal display panel (2), a metal backlight chassis (4), a metal bezel (13), a printed circuit board (31), an electric conductor (14) via which the metal backlight chassis (4) and a ground land part (31f) of the printed circuit board (31) are electrically connected with each other, and a frame (10) having an insertion hole in which the electric conductor (14) is inserted.

Abstract: In a semiconductor integrated circuit device, a first control signal outputted from the power voltage evaluation circuit controls power voltage of the power voltage generation circuit so that the power voltage becomes lower within a range over which the internal circuit normally operates, while a second control signal outputted from the specified voltage detection circuit controls the power voltage of the power voltage generation circuit so that the power voltage generated by the power voltage generation circuit does not become equal to or higher than a specified voltage. This makes the power voltage as low as possible within the normally operational range of the internal circuit and suppresses increase of the gate current, so that unstable operations and current consumption increase of the MOS transistor can be prevented.

Abstract: In a semiconductor integrated circuit device, a first control signal outputted from the power voltage evaluation circuit (12) controls power voltage of the power voltage generation circuit (11) so that the power voltage becomes lower within a range over which the internal circuit normally operates, while a second control signal outputted from the specified voltage detection circuit (13) controls the power voltage of the power voltage generation circuit (11) so that the power voltage generated by the power voltage generation circuit (11) does not become equal to or higher than a specified voltage. This makes the power voltage as low as possible within the normally operational range of the internal circuit (14) and suppresses increase of the gate current, so that unstable operations and current consumption increase of the MOS transistor can be prevented.

Abstract: A digital matched filter has a serial-to-parallel conversion circuit that converts input data fed thereto in serial form into n sets of parallel data and a plurality of delay circuits that each output serial data fed thereto with a delay corresponding to n sets of data. The serial-to-parallel conversion circuit and the delay circuits are each fed with n clocks having different phases, and are composed of delay devices connected in n groups of serially connected delay devices so that the input data is shifted in synchronism with the rising edges of those n clocks. The outputs from the individual delay devices are multiplied by codes by multipliers, and the results of those multiplications are added together and output as output data by an adder.

Abstract: A matched filter has a circuit calculating an exclusive-OR of two input data, a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively, and a correlation processor. The correlation processor, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.

Abstract: A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10−10 A/&mgr;m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10−12 A/&mgr;m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

Abstract: A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10−10 A/&mgr;m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10−12 A/&mgr;m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

Abstract: A matched filter has a circuit calculating an exclusive-OR of two input data, a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively, and a correlation processor. The correlation processor, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.

Abstract: A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10−10 A/&mgr;m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10−12 A/&mgr;m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

Abstract: A variable-length coding device includes: a code presence/absence determination table storing information concerning whether a code is allocated or not correspondingly to a prescribed region in a region represented by a combination of run data and level data; a first region determination circuit and a second region determination circuit determining whether a pair of run data and level data is contained in the prescribed region; and a run.

Abstract: A discrete cosine transformer capable of real time processing without a multiplier having small circuit scale and small power consumption includes an adder/subtractor receiving a plurality of image data items for outputting a plurality of image data item addition/subtraction values in accordance with a prescribed rule, a bit distributor connected to the adder/subtractor, receiving the plurality of image data item addition/subtraction values for outputting a plurality of bit trains consisting of bits at same bit position of the plurality of image data item addition/subtraction values, a selection signal generating circuit for successively generating a selection signal of a DCT coefficient, and a DCT coefficient generating circuit connected to the bit distributor and to the selection signal generating circuit, receiving a plurality of bit trains and responsive to the successively generated selection signal, for performing calculation of the DCT coefficient in time-divisional manner.

Abstract: A logic circuit device includes a superconductive body formed of a ceramic superconductive material. The ceramic superconductive material has random grain boundaries which act as weak couplings. The ceramic superconductive material also has a magneto-resistive property. There is at least one conductor arranged near the ceramic superconductive body in order to exert a magnetic field on the ceramic superconductive body. The ceramic superconductive body changes its resistance in response to the magnetic field generated by the conductor. The ceramic superconductive body can be used as part of a logic circuit.

Abstract: A semiconductor device is disclosed which comprises a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET, wherein all of the components are formed on a single semiconductor chip.

Abstract: A semiconductor device is disclosed which comprises a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET, wherein all of the components are formed on a single semiconductor chip.