Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat.

Abstract: A semiconductor memory device has a plurality of divided memory blocks, each of which has its X-system addresses assigned so that an equal number of word lines in a plurality of sets of memory mats and sense amplifiers may be selected. Each memory block is equipped with a plurality of internal voltage drop circuits for generating a supply voltage from the outside into the operating voltages of the sense amplifiers.

Abstract: An output circuit is provided which includes a first switch coupled between a first power supply terminal and an output terminal, a second switch coupled between the first power supply terminal and the output terminal, an arrangement to set the output terminal at a high impedance state, and a first variable delay coupled to a first input terminal for turning on the first switch and the second switch with different timing from each other and for turning off the first switch and the second switch simultaneously. In addition, the output circuit includes a third switch coupled between the output terminal and a second power supply terminal, a fourth switch coupled between the output terminal and the second power supply terminal, and a second variable delay coupled to a second input terminal for turning on the third switch and the fourth switch with different timing from each other and for turning off the third switch and the fourth switch simultaneously.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.