Patents by Inventor Shinji Ujita
Shinji Ujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11515412Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.Type: GrantFiled: September 21, 2020Date of Patent: November 29, 2022Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
-
Publication number: 20220157980Abstract: A field-effect transistor includes a substrate having conductivity and made of gallium nitride, a buffer layer provided on the substrate and made of C-doped GaN, a drift layer provided on the buffer layer and made of undoped GaN, and a channel layer provided on the drift layer, made of undoped AlGaN, and joined to the drift layer by heterojunction. A gate electrode is provided on the channel layer. A source electrode and a drain electrode are each provided in regions on both sides of the gate electrode on the channel layer.Type: ApplicationFiled: August 5, 2019Publication date: May 19, 2022Inventors: Shinji UJITA, Satoshi TAMURA, Masahiro OGAWA, Daisuke SHIBATA, Hiroyuki HANDA
-
Patent number: 11329175Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.Type: GrantFiled: January 15, 2019Date of Patent: May 10, 2022Assignee: Panasonic Holdings CorporationInventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
-
Publication number: 20210005742Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Applicant: Panasonic CorporationInventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
-
Publication number: 20200411706Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.Type: ApplicationFiled: January 15, 2019Publication date: December 31, 2020Applicant: Panasonic CorporationInventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
-
Patent number: 10818815Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.Type: GrantFiled: July 2, 2019Date of Patent: October 27, 2020Assignee: PANASONIC CORPORATIONInventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
-
Patent number: 10686042Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.Type: GrantFiled: August 6, 2018Date of Patent: June 16, 2020Assignee: PANASONIC CORPORATIONInventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
-
Publication number: 20190326465Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: PANASONIC CORPORATIONInventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
-
Publication number: 20180350917Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Inventors: Shinji UJITA, Daisuke SHIBATA, Satoshi TAMURA
-
Patent number: 9966945Abstract: A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.Type: GrantFiled: July 15, 2016Date of Patent: May 8, 2018Assignee: PANASONIC CORPORATIONInventors: Shinji Ujita, Hiroshi Inada, Tatsuo Morita
-
Patent number: 9654001Abstract: A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode.Type: GrantFiled: October 20, 2015Date of Patent: May 16, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shinji Ujita, Tatsuo Morita
-
Publication number: 20160329890Abstract: A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: SHINJI UJITA, HIROSHI INADA, TATSUO MORITA
-
Publication number: 20160043643Abstract: A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: SHINJI UJITA, TATSUO MORITA
-
Patent number: 8575731Abstract: A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun.Type: GrantFiled: June 15, 2009Date of Patent: November 5, 2013Assignee: Panasonic CorporationInventors: Shinji Ujita, Takeshi Fukuda, Hiroyuki Sakai
-
Patent number: 8492895Abstract: A semiconductor chip such as an MMIC is provided. The semiconductor chip has: a Si semiconductor as a substrate; and a low-loss transmission line, and can be easily connected to a circuit board on which the semiconductor chip is to be mounted and can ensure a stable GND potential. The semiconductor chip is a flip-chip semiconductor chip, and includes: a Si substrate; an integrated circuit manufactured on a main surface of the substrate; a dielectric film formed above the integrated circuit; and a conductor film for grounding formed on an upper surface of the dielectric film. The integrated circuit includes a wiring layer including a signal line which transmits signals for the integrated circuit. The signal line, the dielectric film, and the conductor film constitute a microstrip line.Type: GrantFiled: August 10, 2011Date of Patent: July 23, 2013Assignee: Panasonic CorporationInventors: Hiroyuki Sakai, Takeshi Fukuda, Shinji Ujita, Yasufumi Kawai
-
Patent number: 8471645Abstract: A balanced-unbalanced transformer includes: a balanced transmission line including paired transmission lines; an unbalanced transmission line; and two lead transmission lines connected to two neighboring end portions of four end portions of the paired transmission lines at a right angle to the paired transmission lines, wherein one of the two lead transmission lines has a first electrode face which faces the other of the two lead transmission lines, the other of the two lead transmission lines has a second electrode face which faces the one of the two lead transmission lines, and the first electrode face and the second electrode face are electrode faces of a capacitor.Type: GrantFiled: December 6, 2012Date of Patent: June 25, 2013Assignee: Panasonic CorporationInventors: Shinji Ujita, Hiroyuki Sakai
-
Publication number: 20110291271Abstract: A semiconductor chip such as an MMIC is provided. The semiconductor chip has: a Si semiconductor as a substrate; and a low-loss transmission line, and can be easily connected to a circuit board on which the semiconductor chip is to be mounted and can ensure a stable GND potential. The semiconductor chip is a flip-chip semiconductor chip, and includes: a Si substrate; an integrated circuit manufactured on a main surface of the substrate; a dielectric film formed above the integrated circuit; and a conductor film for grounding formed on an upper surface of the dielectric film. The integrated circuit includes a wiring layer including a signal line which transmits signals for the integrated circuit. The signal line, the dielectric film, and the conductor film constitute a microstrip line.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Hiroyuki SAKAI, Takeshi FUKUDA, Shinji UJITA, Yasufumi KAWAI
-
Publication number: 20110089543Abstract: A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun.Type: ApplicationFiled: June 15, 2009Publication date: April 21, 2011Applicant: PANASONIC CORPORATIONInventors: Shinji Ujita, Takeshi Fukuda, Hiroyuki Sakai
-
Patent number: 7898469Abstract: Provided is a receiving device that is used for a spread spectrum radar apparatus, receives a spectrum-spread signal, and obtains a precise radar spectrum, and includes: a despreading unit that (i) generates first and second despread signals that are generated by despreading a reception signal using a pseudo-noise code, the second despread signal passing through a transmission line carrying a current having a current value identical to a current value of a current carried by a transmission line through which the first despread signal passes, and (ii) includes a first transistor pair including first and second transistors having an identical characteristic, the first transistor outputting the first despread signal, and the second transistor outputting the second despread signal; and a quadrature demodulating unit that generates an in-phase signal and a quadrature signal by quadrature-demodulating the first despread signal and the second despread signal, respectively.Type: GrantFiled: September 25, 2008Date of Patent: March 1, 2011Assignee: Panasonic CorporationInventors: Shinji Ujita, Takeshi Fukuda
-
Publication number: 20090091491Abstract: Provided is a receiving device that is used for a spread spectrum radar apparatus, receives a spectrum-spread signal, and obtains a precise radar spectrum, and includes: a despreading unit that (i) generates first and second despread signals that are generated by despreading a reception signal using a pseudo-noise code, the second despread signal passing through a transmission line carrying a current having a current value identical to a current value of a current carried by a transmission line through which the first despread signal passes, and (ii) includes a first transistor pair including first and second transistors having an identical characteristic, the first transistor outputting the first despread signal, and the second transistor outputting the second despread signal; and a quadrature demodulating unit that generates an in-phase signal and a quadrature signal by quadrature-demodulating the first despread signal and the second despread signal, respectively.Type: ApplicationFiled: September 25, 2008Publication date: April 9, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shinji UJITA, Takeshi FUKUDA