Patents by Inventor Shinji YAMASHINA

Shinji YAMASHINA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10620650
    Abstract: A semiconductor device having an input terminal and an output terminal. The semiconductor device includes a power semiconductor element having a first main terminal connected to the output terminal, a second main terminal that is grounded and a gate terminal, and an active clamping circuit including a Zener diode and a diode connected in inverse series between the gate terminal and the first main terminal of the power semiconductor element. The semiconductor device further includes a clamp voltage switching circuit configured to switch a clamp voltage of the active clamping circuit according to a change in a voltage of the output terminal relative to the ground at a time when the power semiconductor element is turned off, the clamp voltage being switched to a first clamp voltage and a second clamp voltage, respectively, when the change in the voltage is not, and is, positive.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Morio Iwamizu, Shinji Yamashina
  • Publication number: 20190286181
    Abstract: A semiconductor device having an input terminal and an output terminal. The semiconductor device includes a power semiconductor element having a first main terminal connected to the output terminal, a second main terminal that is grounded and a gate terminal, and an active clamping circuit including a Zener diode and a diode connected in inverse series between the gate terminal and the first main terminal of the power semiconductor element. The semiconductor device further includes a clamp voltage switching circuit configured to switch a clamp voltage of the active clamping circuit according to a change in a voltage of the output terminal relative to the ground at a time when the power semiconductor element is turned off, the clamp voltage being switched to a first clamp voltage and a second clamp voltage, respectively, when the change in the voltage is not, and is, positive.
    Type: Application
    Filed: January 29, 2019
    Publication date: September 19, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Morio IWAMIZU, Shinji YAMASHINA
  • Patent number: 9490793
    Abstract: An insulated-gate type device driving circuit for driving an insulated-gate semiconductor element based on a gate signal inputted from the outside includes a gate voltage control semiconductor element which is connected between a gate and a source of the insulated-gate semiconductor element, and a pull-up element which is constituted by a depletion type MOSFET connected between a gate and a drain of the gate voltage control semiconductor element. The gate voltage control semiconductor element is driven by a voltage applied to the gate of the insulated-gate semiconductor element, and a back gate of the MOSFET constituting the pull-up element is grounded to prevent a parasitic transistor from being formed.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: November 8, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Morio Iwamizu, Shinji Yamashina
  • Publication number: 20150263719
    Abstract: An insulated-gate type device driving circuit for driving an insulated-gate semiconductor element based on a gate signal inputted from the outside includes a gate voltage control semiconductor element which is connected between a gate and a source of the insulated-gate semiconductor element, and a pull-up element which is constituted by a depletion type MOSFET connected between a gate and a drain of the gate voltage control semiconductor element. The gate voltage control semiconductor element is driven by a voltage applied to the gate of the insulated-gate semiconductor element, and a back gate of the MOSFET constituting the pull-up element is grounded to prevent a parasitic transistor from being formed.
    Type: Application
    Filed: February 12, 2015
    Publication date: September 17, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Morio IWAMIZU, Shinji YAMASHINA