Patents by Inventor Shinji Yamaura
Shinji Yamaura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11855338Abstract: A radar device includes: a transmitting antenna having at least one element antenna; and a receiving antenna having a plurality of element antennas. The plurality of element antennas of the receiving antenna are arranged at different positions in a first direction and a second direction perpendicular to the first direction. A distance between two adjacent element antennas among the plurality of element antennas of the receiving antenna in the first direction is equal to each other. A distance between two adjacent element antennas among the plurality of element antennas of the receiving antenna in the second direction is equal to each other.Type: GrantFiled: April 22, 2021Date of Patent: December 26, 2023Assignee: DENSO CORPORATIONInventor: Shinji Yamaura
-
Publication number: 20210242577Abstract: A radar device includes: a transmitting antenna having at least one element antenna; and a receiving antenna having a plurality of element antennas. The plurality of element antennas of the receiving antenna are arranged at different positions in a first direction and a second direction perpendicular to the first direction. A distance between two adjacent element antennas among the plurality of element antennas of the receiving antenna in the first direction is equal to each other. A distance between two adjacent element antennas among the plurality of element antennas of the receiving antenna in the second direction is equal to each other.Type: ApplicationFiled: April 22, 2021Publication date: August 5, 2021Inventor: Shinji YAMAURA
-
Publication number: 20190170857Abstract: A radar transceiver may include a noise canceller. The noise canceller may include a phase shifter circuit, a variable gain amplifier, and a coupler circuit. The phase shifter circuit may shift (i) a phase of a modulated signal, (ii) a phase of an original signal, or (iii) a phase of a signal generated by a noise cancellation signal generator circuit having a frequency corresponding to a frequency of a reflected signal which is reflected by an obstacle. The variable gain amplifier may amplify or attenuate a noise cancellation signal. The coupler circuit may couple the noise cancellation signal with a received signal from a receiver. An amplitude of the noise cancellation signal may be controlled by a controller via the variable gain amplifier. A phase shift amount of the noise cancellation signal may be controlled by the controller via the phase shifter circuit.Type: ApplicationFiled: February 6, 2019Publication date: June 6, 2019Inventors: Kensuke NAKAJIMA, Shinji YAMAURA
-
Patent number: 9614482Abstract: An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, and the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.Type: GrantFiled: September 9, 2014Date of Patent: April 4, 2017Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoichi Kawano, Shinji Yamaura
-
Patent number: 9148091Abstract: In a power amplifier including an amplifier circuit unit for high power mode and an amplifier circuit unit for low power mode provided in parallel thereto between input and output of the amplifier and where, when one amplifier circuit unit is in an operating state, the other amplifier circuit unit is in a non-operating state, a cross-coupled capacitor is provided between a drain of one of two transistors in output side and a gate of the other transistor in the amplifier circuit unit for high power mode, and a series circuit where a switch and a capacitor are coupled in series is coupled between a drain of the transistor of output side in the amplifier circuit unit for low power mode and a ground, the switch being in a conducting state in high power mode operation and being in a non-conducting state in low power mode operation.Type: GrantFiled: January 31, 2014Date of Patent: September 29, 2015Assignee: SOCIONEXT INC.Inventors: Tomoaki Sato, Shinji Yamaura
-
Publication number: 20150097619Abstract: An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, end the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.Type: ApplicationFiled: September 9, 2014Publication date: April 9, 2015Inventors: Yoichi Kawano, Shinji Yamaura
-
Publication number: 20140227988Abstract: In a power amplifier including an amplifier circuit unit for high power mode and an amplifier circuit unit for low power mode provided in parallel thereto between input and output of the amplifier and where, when one amplifier circuit unit is in an operating state, the other amplifier circuit unit is in a non-operating state, a cross-coupled capacitor is provided between a drain of one of two transistors in output side and a gate of the other transistor in the amplifier circuit unit for high power mode, and a series circuit where a switch and a capacitor are coupled in series is coupled between a drain of the transistor of output side in the amplifier circuit unit for low power mode and a ground, the switch being in a conducting state in high power mode operation and being in a non-conducting state in low power mode operation.Type: ApplicationFiled: January 31, 2014Publication date: August 14, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tomoaki SATO, Shinji YAMAURA
-
Patent number: 8604955Abstract: In order to suppress the enlargement of the circuit layout area of an LSI together with the cost, even at the time when the variation width of the filter characteristic is narrow within a wide range, a filter varies an element value of at least one kind of elements (3), which determine a filter characteristic of the filter circuit, according to an output of the sigma-delta modulator (1), which sigma-delta modulates a digital code input (Code), according to an operation clock (CLK), or according to a signal through a decoder (4), which performs a code-conversion to an output of the sigma-delta modulator (1).Type: GrantFiled: January 12, 2011Date of Patent: December 10, 2013Assignee: Fujitsu LimitedInventors: Kazuaki Oishi, Shinji Yamaura
-
Patent number: 8283980Abstract: An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.Type: GrantFiled: September 25, 2009Date of Patent: October 9, 2012Assignee: Fujitsu LimitedInventors: Tomoyuki Arai, Masahiro Kudo, Shinji Yamaura
-
Publication number: 20110170628Abstract: In order to suppress the enlargement of the circuit layout area of an LSI together with the cost, even at the time when the variation width of the filter characteristic is narrow within a wide range, a filter varies an element value of at least one kind of elements (3), which determine a filter characteristic of the filter circuit, according to an output of the sigma-delta modulator (1), which sigma-delta modulates a digital code input (Code), according to an operation clock (CLK), or according to a signal through a decoder (4), which performs a code-conversion to an output of the sigma-delta modulator (1).Type: ApplicationFiled: January 12, 2011Publication date: July 14, 2011Applicant: FUJITSU LIMITEDInventors: Kazuaki OISHI, Shinji Yamaura
-
Patent number: 7675360Abstract: A power control circuit includes: a fine adjustment variable amplifying unit configured to amplify the input signal in accordance with a first gain set value; a coarse adjustment variable amplifying unit configured to amplify the input signal in accordance with a second gain set value; a branching unit configured to branch an output signal into a feedback signal; a comparing unit configured to compare a gain value between the input signal and the output signal with the required gain set value; a control unit configured to determine the first gain set value and the second gain set value based on the required gain set value; and an adjusting unit configured to adjust the first gain set value and the second gain set value so that the power value of the feedback signal becomes a power value corresponding to the required gain set value.Type: GrantFiled: October 3, 2008Date of Patent: March 9, 2010Assignee: Fujitsu LimitedInventors: Tomoyuki Arai, Takao Sasaki, Shinji Yamaura
-
Publication number: 20100039178Abstract: An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.Type: ApplicationFiled: September 25, 2009Publication date: February 18, 2010Applicant: FUJITSU LIMITEDInventors: Tomoyuki ARAI, Masahiro KUDO, Shinji YAMAURA
-
Publication number: 20090167435Abstract: A power control circuit includes: a fine adjustment variable amplifying unit configured to amplify the input signal in accordance with a first gain set value; a coarse adjustment variable amplifying unit configured to amplify the input signal in accordance with a second gain set value; a branching unit configured to branch an output signal into a feedback signal; a comparing unit configured to compare a gain value between the input signal and the output signal with the required gain set value; a control unit configured to determine the first gain set value and the second gain set value based on the required gain set value; and an adjusting unit configured to adjust the first gain set value and the second gain set value so that the power value of the feedback signal becomes a power value corresponding to the required gain set value.Type: ApplicationFiled: October 3, 2008Publication date: July 2, 2009Applicant: FUJITSU LIMITEDInventors: Tomoyuki Arai, Takao Sasaki, Shinji Yamaura
-
Patent number: 5738722Abstract: The invention relates to a method for manufacturing a III-V system compound semiconductor device, provides such a new C dopant as alkyl halide (CH.sub.2 I.sub.2 for example) containing carbon (C), iodine (I), and hydrogen (H) for giving a highly p-type conductivity to a GaAs crystal layer, an InGaAs crystal layer or the like as an object of it, and includes a process of forming a p-type III-V system compound semiconductor layer as using a compound containing carbon (C) as a dopant material for giving a p-type conductivity and further containing iodine (I) and hydrogen (H) as impurity.Type: GrantFiled: August 31, 1995Date of Patent: April 14, 1998Assignee: Fujitsu LimitedInventors: Takeshi Tomioka, Hideyasu Ando, Naoya Okamoto, Shinji Yamaura
-
Patent number: 5479028Abstract: The invention relates to a method for manufacturing a III-V system compound semiconductor device, provides such a new C dopant as alkyl halide (CH.sub.2 I.sub.2 for example) containing carbon (C), iodine (I), and hydrogen (H) for giving a highly p-type conductivity to a GaAs crystal layer, an InGaAs crystal layer or the like as an object of it, and includes a process of forming a p-type III-V system compound semiconductor layer as using a compound containing carbon (C) as a dopant material for giving a p-type conductivity and further containing iodine (I) and hydrogen (H) as impurity.Type: GrantFiled: September 27, 1994Date of Patent: December 26, 1995Assignee: Fujitsu LimitedInventors: Takeshi Tomioka, Hideyasu Ando, Naoya Okamoto, Shinji Yamaura