Patents by Inventor Shinji Yoda
Shinji Yoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10493547Abstract: Whether or not an inter-electrode voltage exceeds a voltage threshold is determined after a predetermined inter-electrode state determination period has passed since application of an induction voltage (inter-electrode voltage) to an inter-electrode gap. Thus, an inter-electrode gap amount between a wire electrode and a work is estimated. A pause time during which electrical discharge is not performed is changed according to an estimation result of the inter-electrode gap amount.Type: GrantFiled: April 14, 2017Date of Patent: December 3, 2019Assignee: FANUC CORPORATIONInventors: Shinji Yoda, Tomoyuki Furuta, Tomoaki Matsunaga
-
Patent number: 9950378Abstract: In a wire electric discharge machine, a discharge delay time is used to classify the inter-electrode state into three categories; a short-circuit state, small-gap state, and large-gap state. Based on this classification, the magnitude of a machining current supplied from a main discharge circuit is determined. If the discharge delay time is zero (i.e., if no electric discharge is generated) after the lapse of a predetermined time since the start of the application of a machining voltage to an inter-electrode gap by an auxiliary discharge circuit, the inter-electrode gap is determined to be short-circuited by machining chips. Thereupon, a short-circuit machining current is supplied from the main discharge circuit to the inter-electrode gap to remove the machining chips. In this way, establishment of a complete short-circuit state is prevented so that the machining efficiency is improved to increase the machining speed.Type: GrantFiled: April 1, 2016Date of Patent: April 24, 2018Assignee: FANUC CORPORATIONInventors: Tomoyuki Furuta, Shinji Yoda, Akiyoshi Kawahara, Yasuo Nakashima
-
Publication number: 20170297126Abstract: Whether or not an inter-electrode voltage exceeds a voltage threshold is determined after a predetermined inter-electrode state determination period has passed since application of an induction voltage (inter-electrode voltage) to an inter-electrode gap. Thus, an inter-electrode gap amount between a wire electrode and a work is estimated. A pause time during which electrical discharge is not performed is changed according to an estimation result of the inter-electrode gap amount.Type: ApplicationFiled: April 14, 2017Publication date: October 19, 2017Inventors: Shinji YODA, Tomoyuki FURUTA, Tomoaki MATSUNAGA
-
Publication number: 20160288230Abstract: In a wire electric discharge machine, a discharge delay time is used to classify the inter-electrode state into three categories; a short-circuit state, small-gap state, and large-gap state. Based on this classification, the magnitude of a machining current supplied from a main discharge circuit is determined. If the discharge delay time is zero (i.e., if no electric discharge is generated) after the lapse of a predetermined time since the start of the application of a machining voltage to an inter-electrode gap by an auxiliary discharge circuit, the inter-electrode gap is determined to be short-circuited by machining chips. Thereupon, a short-circuit machining current is supplied from the main discharge circuit to the inter-electrode gap to remove the machining chips. In this way, establishment of a complete short-circuit state is prevented so that the machining efficiency is improved to increase the machining speed.Type: ApplicationFiled: April 1, 2016Publication date: October 6, 2016Inventors: Tomoyuki FURUTA, Shinji YODA, Akiyoshi KAWAHARA, Yasuo NAKASHIMA
-
Patent number: 9301342Abstract: A heater wire is obtained by twisting together a plurality of heating element wires in which a rectangular wire is spirally wound around a core wire, and forming an insulating sheath on an outer peripheral surface of the twisted heating element wires. The current carrying capacity can be increased by increasing the number of the heating element wires and there is no need of increasing the cross-sectional area of each of the rectangular wires. Therefore, a reduction in the bending capacity due to an increase in the cross-sectional area of the rectangular wires can be avoided, and the bending capacity can be improved significantly.Type: GrantFiled: May 16, 2012Date of Patent: March 29, 2016Assignee: Totoku Electric Co., Ltd.Inventors: Shohei Miyahara, Yuichi Nakajo, Shigeo Hayashi, Shinji Yoda
-
Publication number: 20140091081Abstract: A heater wire is obtained by twisting together a plurality of heating element wires in which a rectangular wire is spirally wound around a core wire, and forming an insulating sheath on an outer peripheral surface of the twisted heating element wires, The current carrying capacity can be increased by increasing the number of the heating element wires and there is no need of increasing the cross-sectional area of each of the rectangular wires, Therefore, a reduction in the bending capacity due to an increase in the cross-sectional area of the rectangular wires can be avoided, and the bending capacity can be improved significantly.Type: ApplicationFiled: May 16, 2012Publication date: April 3, 2014Inventors: Shohei Miyahara, Yuichi Nakajo, Shigeo Hayashi, Shinji Yoda
-
Publication number: 20040165723Abstract: An image processing apparatus, an image processing system, and an image information transmission method which are high in a secrecy nature in transmission of image information are provided.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Applicant: TOSHIBA TEC KABUSHIKI KAISHAInventors: Shinji Yoda, Takuya Kotsuji
-
Patent number: 5946036Abstract: A coding data is performed in decoding by a stream decoding circuit, an IDCT circuit and an MC circuit. An AGU stores decoding data from the MC circuit to a memory. Regarding the decoding data of a B picture, the AGU writes only the decoding data which are necessary for image display, to a B picture region. Thus, a room occurs in a memory capacity. It is possible to hold the decoding data of the B picture through 2 field periods of time. It is possible to read twice the same decoding data, for display processing. Thus, frame interpolation processing is made possible, and it is possible to obtain a magnified image having high image quality.Type: GrantFiled: January 8, 1997Date of Patent: August 31, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kouichi Kurihara, Shuji Abe, Shinji Yoda
-
Patent number: 5784526Abstract: When the low bit rate coding is effected in a recording system 1A, a signal is coded and recorded in a hierarchical structure. On the reproduction side, the type of a recorded signal (the low bit rate coded signal of the hierarchical structure, non-hierarchical structure, conventional analog recording or the like) is determined by a determination system 1E and the operation modes of a digital signal processing system 1G and an analog signal processing system 1F are set. The analog signal processing system processes a reproduced signal when it is analog signal. The digital signal processing system processes a reproduced signal when it is a digital signal or when a reproduced output from the analog signal processing system is processed in a digital manner.Type: GrantFiled: October 31, 1994Date of Patent: July 21, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shimoda, Hideo Tsurufusa, Shinji Yoda, Kazuyoshi Fuse
-
Patent number: 5753880Abstract: A method of recovering a wire breakage in a wire electric discharge machine in which a wire is automatically connected through a machining groove near a wire breakage position to reduce a time from the wire breakage to the restarting of the electric discharge machining. After detecting the wire breakage, the wire is automatically connected at an intermediate position between the wire breakage position and a start point of a machining block in which the wire breakage occurred under the conditions that the machining block is of a straight-line command or of a circular-arc command having a radius larger than a set radius r0 and a length D between the wire breakage position and a start point of the machining block is equal to or larger than a set length D0.Type: GrantFiled: January 10, 1997Date of Patent: May 19, 1998Assignee: Fanuc Ltd.Inventors: Toyotada Kajitori, Shinji Yoda
-
Patent number: 5754243Abstract: A read control circuit reads image data, which are stored in a decoding image memory, at a read speed m/n times a display speed. These image data are written to line memories by a write control circuit. A read-address control circuit reads the image data from the line memories at a display speed, and line data for a letter-box image are generated by multipliers and an adder. Specifically, the line data of m lines which are read from the decoding image memory are transformed to n lines so that a letter-box display is made possible. Thus, letter-box transformation processing is performed with less memory capacity without the use of a field memory.Type: GrantFiled: February 25, 1997Date of Patent: May 19, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kouichi Kurihara, Shuji Abe, Takeshi Inagaki, Shinji Yoda
-
Patent number: 5561608Abstract: When the low bit rate coding is effected in a recording system 1A, a signal is coded and recorded in a hierarchical structure. On the reproduction side, the type of a recorded signal (the low bit rate coded signal of the hierarchical structure, non-hierarchical structure, conventional analog recording or the like) is determined by a determination system 1E and the operation modes of a digital signal processing system 1G and an analog signal processing system 1F are set. The analog signal processing system processes a reproduced signal when it is analog signal. The digital signal processing system processes a reproduced signal when it is a digital signal or when a reproduced output from the analog signal processing system is processed in a digital manner.Type: GrantFiled: February 10, 1995Date of Patent: October 1, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shimoda, Hideo Tsurufusa, Shinji Yoda, Kazuyoshi Fuse
-
Patent number: 5394249Abstract: When the low bit rate coding is effected in a recording system 1A, a signal is coded and recorded in a hierarchical structure. On the reproduction side, the type of a recorded signal (the low bit rate coded signal of the hierarchical structure, non-hierarchical structure, conventional analog recording or the like) is determined by a determination system 1E and the operation modes of a digital signal processing system 1G and an analog signal processing system 1F are set. The analog signal processing system processes a reproduced signal when it is analog signal. The digital signal processing system processes a reproduced signal when it is a digital signal or when a reproduced output from the analog signal processing system is processed in a digital manner.Type: GrantFiled: July 12, 1993Date of Patent: February 28, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shimoda, Hideo Tsurufusa, Shinji Yoda, Kazuyoshi Fuse
-
Patent number: 5183987Abstract: A method and an apparatus for easily and reliably removing cut-out pieces cut out from a workpiece by wire-cut electric discharge machining, in which, upon completion of cutting a piece (41) out, a constraining assembly (63) mounted on the distal end of a piston (62) is brought close to the top surface of the piece under the control of a numerical control unit, and machining fluid is upwardly jetted from a lower nozzle (19) toward the bottom surface of the piece, to thereby hold the piece in the workpiece, with the piece kept away from the lower nozzle and prevented from being detached upwardly from the workpiece. While jetting the machining fluid, a worktable is horizontally moved to cause the cut-out piece to move in unison with the workpiece away from the lower nozzle in the horizontal direction.Type: GrantFiled: December 5, 1991Date of Patent: February 2, 1993Assignee: Fanuc Ltd.Inventors: Toshiyuki Aso, Shinji Yoda
-
Patent number: 5164563Abstract: A core removing apparatus for removing cores from a workpiece upwardly or downwardly in dependence on the shape of each core cut out from the workpiece by means of wire-cut electric discharge machinng comprises a core removing unit (6) mounted on an electric discharge machine body. When a first operation mode is selected according to a code read from a program after a core (20) having an inverted trapezoidal shape in cross section is taper-machined, a core sucking section (16), fixed to the piston (15) of a vertical cylinder of the core removing unit, is brought in contact with the core by vertical movement and rotation of the piston, and the sucking section by which the core is sucked and held is moved upwardly to thereby pull out the core from the workpiece (19). Then, the core, moved to the outside of a core falling prohibition region by horizontal movement of the piston (13) of the horizontal cylinder, is disengaged from the core sucking section.Type: GrantFiled: November 18, 1991Date of Patent: November 17, 1992Assignee: Fanuc, Ltd.Inventors: Toshiyuki Aso, Shinji Yoda
-
Patent number: 4951137Abstract: Image track display apparatus including a memory for delaying an image signal by at least one vertical scanning period, a first subtraction circuit for taking a first difference signal between the image signal and its delayed image signal through the memory. The first difference signal includes first and second polarity components, a non-linear processing circuit for multiplying the one polarity component of the first difference signal by K times (0<K<1) and for reducing the other polarity component of the first difference signal to the zero value when the other polarity component exceeds a prescribed value, a second subtraction circuit for taking a second difference signal between the output signal of the non-linear processing circuit and the image signal, and a display device for displaying the delayed image signal obtained through the memory circuit.Type: GrantFiled: March 31, 1989Date of Patent: August 21, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Kisou, Kenji Shimoda, Kazumasa Ikeda, Shinji Yoda, Hisaharu Takeuchi