Abstract: A first contact hole is formed penetrating a gate insulating film, on which a gate electrode is formed and simultaneously a first contact is formed in the first contact hole. A second contact hole penetrating an interlayer insulating film is formed, and a second contact is formed in the second contact hole. A third contact hole is formed penetrating a planarization film, and an electrode is formed in the third contact hole. By using a plurality of contact holes for electrically connecting the electrode and a semiconductor film, the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1?(T2×8000 ?) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: A first contact hole (6) is formed penetrating a gate insulating film (5), on which a gate electrode (7g) is formed and simultaneously a first contact (7s, 7d) is formed in the first contact hole. A second contact hole (9) penetrating an interlayer insulating film (8) is formed, and a second contact (10) is formed in the second contact hole (9). A third contact hole (11) is formed penetrating a planarization film (26), and an electrode (40) is formed in the third contact hole (11). By using a plurality of contact holes for electrically connecting the electrode (40) and a semiconductor film (3), the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.