Patents by Inventor Shinjiro Kameda
Shinjiro Kameda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840277Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.Type: GrantFiled: July 31, 2013Date of Patent: November 17, 2020Assignee: Sony Semiconductor Solutions CorporationInventors: Shinjiro Kameda, Eiichi Funatsu
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Patent number: 9490291Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: June 23, 2015Date of Patent: November 8, 2016Assignee: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20150334270Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: June 23, 2015Publication date: November 19, 2015Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 9129879Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: September 24, 2013Date of Patent: September 8, 2015Assignee: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20150249798Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (OV), and a negative power source potential (for example ?1V).Type: ApplicationFiled: February 26, 2015Publication date: September 3, 2015Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20130313673Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: Sony CorporationInventors: Shinjiro KAMEDA, Eiichi FUNATSU
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Patent number: 8558932Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: November 14, 2011Date of Patent: October 15, 2013Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 8519502Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.Type: GrantFiled: July 6, 2007Date of Patent: August 27, 2013Assignee: Sony CorporationInventors: Shinjiro Kameda, Eiichi Funatsu
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Patent number: 8227734Abstract: There is provided a solid-state imaging device including: a plurality of aperture pixels configured to be used for capturing of an image; a plurality of first light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the first light-shielded pixels being larger than a temperature dependence of a dark current in the aperture pixels; and a plurality of second light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the second light-shielded pixels being smaller than a temperature dependence of a dark current in the aperture pixels.Type: GrantFiled: February 5, 2008Date of Patent: July 24, 2012Assignee: Sony CorporationInventor: Shinjiro Kameda
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Publication number: 20120105698Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: November 14, 2011Publication date: May 3, 2012Applicant: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 8072528Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: November 30, 2009Date of Patent: December 6, 2011Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20100073536Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 7626625Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: September 16, 2004Date of Patent: December 1, 2009Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20080197268Abstract: There is provided a solid-state imaging device including: a plurality of aperture pixels configured to be used for capturing of an image; a plurality of first light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the first light-shielded pixels being larger than a temperature dependence of a dark current in the aperture pixels; and a plurality of second light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the second light-shielded pixels being smaller than a temperature dependence of a dark current in the aperture pixels.Type: ApplicationFiled: February 5, 2008Publication date: August 21, 2008Inventor: Shinjiro Kameda
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Publication number: 20080029837Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.Type: ApplicationFiled: July 6, 2007Publication date: February 7, 2008Inventors: Shinjiro Kameda, Eiichi Funatsu