Patents by Inventor Shinjiro Kato

Shinjiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094756
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 21, 2024
    Applicant: ABLIC INC.
    Inventors: Takeshi KOYAMA, Hisashi Hasegawa, Shinjiro Kato, Kohei Kawabata
  • Publication number: 20230317643
    Abstract: Provided is a semiconductor device. The semiconductor device includes a first circuit that includes a plurality of fixed resistance elements connected in series; a second circuit that includes a plurality of variable resistance elements connected in series and that is connected in series to the first circuit; a first cover portion that is provided on an upper layer side of the first circuit and that covers the first circuit; and a second cover portion that is provided on an upper layer side of the second circuit and that covers the second circuit. The first cover portion included two or more first metal films electrically connected, correspondingly, to units having any number of the fixed resistance elements, and the second cover portion includes a second metal film electrically connected to the plurality of the variable resistance elements.
    Type: Application
    Filed: March 17, 2023
    Publication date: October 5, 2023
    Applicant: ABLIC Inc.
    Inventor: Shinjiro KATO
  • Patent number: 11587869
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 21, 2023
    Assignee: ABLIC INC.
    Inventors: Hisashi Hasegawa, Takeshi Koyama, Shinjiro Kato, Kohei Kawabata
  • Publication number: 20220137658
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Inventors: Takeshi KOYAMA, Hisashi HASEGAWA, Shinjiro KATO, Kohei KAWABATA
  • Publication number: 20210134714
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 6, 2021
    Inventors: Hisashi HASEGAWA, Takeshi KOYAMA, Shinjiro KATO, Kohei KAWABATA
  • Patent number: 10978414
    Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 13, 2021
    Assignee: ABLIC INC.
    Inventors: Shinjiro Kato, Masaru Akino
  • Publication number: 20200185343
    Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Inventors: Shinjiro Kato, Masaru AKINO
  • Patent number: 10607954
    Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 31, 2020
    Assignee: ABLIC INC.
    Inventors: Shinjiro Kato, Masaru Akino
  • Patent number: 10586776
    Abstract: A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 10, 2020
    Assignee: ABLIC INC.
    Inventors: Yoichi Mimuro, Shinjiro Kato, Tetsuo Shioura
  • Publication number: 20190261091
    Abstract: A speaker diaphragm includes a protruding dome portion formed at a center portion of the speaker diaphragm, and an annular cone portion extending from an outer peripheral edge of the dome portion in a direction inclined with respect to a protrusion direction of the dome portion. The dome portion and the cone portion are, in a seamless manner, integrally formed of a sheet material made of magnesium or magnesium alloy, and an outer peripheral end of the cone portion at least extends to a substantially identical height position to a maximum protrusion position of the dome portion. An annular step portion for attachment of a cylindrical voice coil bobbin is provided along a boundary portion between the dome portion and the cone portion.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Takeshi FUJITANI, Nanayo SUZUKI, Shinjiro KATO, Tomoyuki SUZUKI
  • Patent number: 10388618
    Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 20, 2019
    Assignee: ABLIC Inc.
    Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Publication number: 20190189575
    Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: Takeshi MORITA, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Patent number: 10327075
    Abstract: A method is provided for manufacturing a speaker diaphragm manufactured using a sheet material made of magnesium or magnesium alloy and including an annular cone portion along an outer peripheral edge of a dome portion. The method includes a dome preformation process of forming a dome preformation portion; a cone preformation process of forming an annular cone preformation portion; and a shaping process of shaping the dome preformation portion into the dome portion by pressing, shaping the cone preformation portion into the cone portion whose outer peripheral end at least extends to a substantially identical height position to a maximum protrusion position of the dome portion, and forming, along a boundary portion between the dome portion and the cone portion, an annular step portion to which a voice coil bobbin is attached.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 18, 2019
    Assignee: Onkyo Corporation
    Inventors: Takeshi Fujitani, Nanayo Suzuki, Shinjiro Kato, Tomoyuki Suzuki
  • Patent number: 10297562
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignee: ABLIC INC.
    Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
  • Patent number: 10249584
    Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 2, 2019
    Assignee: ABLIC INC.
    Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Publication number: 20180269169
    Abstract: A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 20, 2018
    Inventors: Takeshi MORITA, Shinjiro KATO, Masaru AKINO, Yukihiro IMURA
  • Publication number: 20180269170
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 20, 2018
    Inventors: Kaku IGARASHI, Shinjiro KATO, Hisashi HASEGAWA, Masaru AKINO, Yukihiro IMURA
  • Publication number: 20180269171
    Abstract: A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 20, 2018
    Inventors: Shinjiro KATO, Masaru AKINO
  • Publication number: 20180261562
    Abstract: A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 13, 2018
    Inventors: Yoichi MIMURO, Shinjiro KATO, Tetsuo SHIOURA
  • Patent number: 9972625
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 15, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino