Patents by Inventor Shinkuro Sato

Shinkuro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150364646
    Abstract: A crystal layered structure includes a Ga2O3 substrate and a nitride semiconductor layer and is capable of providing a light emitting element having high light output and a light emitting element includes this crystal layered structure. The crystal layered structure includes a Ga2O3 substrate a dielectric layer which is formed on the Ga2O3 substrate so as to partially cover the upper surface of the Ga2O3 substrate, and which has a refractive index difference of 0.15 or less relative to the Ga2O3 substrate and a nitride semiconductor layer which is formed on the Ga2O3 substrate with the dielectric layer interposed therebetween, and which is in contact with the dielectric layer and a portion not covered by the dielectric layer on the upper surface of the Ga2O3 substrate.
    Type: Application
    Filed: December 25, 2013
    Publication date: December 17, 2015
    Applicant: TAMURA CORPORATION
    Inventors: Yoshikatsu MORISHIMA, Shinkuro SATO, Ken GOTO, Kazuyuki IIZUKA, Akito KURAMATA
  • Patent number: 9153648
    Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga2O3 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AlN buffer layer formed on the Ga2O3 substrate, and a nitride semiconductor layer formed on the AlN buffer layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: October 6, 2015
    Assignees: TAMURA CORPORATION, KOHA CO, LTD.
    Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
  • Publication number: 20150249184
    Abstract: A semiconductor multilayer structure includes a ?-Ga2O3-based single crystal substrate including a main surface including a (?201), (101), (310) or (3-10) plane, the ?-Ga2O3-based single crystal substrate being free from any twinning plane or further including a region free from any twinning plane, the region including a maximum width of not less than 2 inches in a direction perpendicular to an intersection line between a twinning plane and the main surface, and a nitride semiconductor layer including an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal epitaxially grown on the ?-Ga2O3-based single crystal substrate.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 3, 2015
    Inventor: Shinkuro SATO
  • Publication number: 20150249189
    Abstract: A semiconductor multilayer structure includes a ?-Ga2O3-based single crystal substrate including a dislocation density on a main surface of not more than 1×103/cm2; and a nitride semiconductor layer including an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal epitaxially grown on the ?-Ga2O3-based single crystal substrate.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 3, 2015
    Inventor: Shinkuro SATO
  • Patent number: 9059077
    Abstract: Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal on the Ga2O3 substrate; and a nitride semiconductor layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y +z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the Ga2O3 substrate is no less than 1.0×1018/cm3.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: June 16, 2015
    Assignees: TAMURA CORPORATION, KOHA CO., LTD
    Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato
  • Publication number: 20150155356
    Abstract: Provided is a semiconductor laminate structure including a Ga2O3 substrate and a nitride semiconductor layer with high crystal quality on the Ga2O3 substrate, and also provided is a semiconductor element including this semiconductor laminate structure. In one embodiment, this semiconductor laminate structure includes a ?-Ga2O3 substrate including ?-Ga2O3 crystal and a principal surface inclined from a (?201) surface to a [102] direction nd a nitride semiconductor layer including AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal formed by epitaxial crystal growth on the principal surface of the ?-Ga2O3 substrate.
    Type: Application
    Filed: May 27, 2013
    Publication date: June 4, 2015
    Applicants: TAMURA CORPORATIO9N, KOHA CO., LTD
    Inventors: Kazuyuki Iizuka, Shinya Watanabe, Kimiyoshi Koshi, Daiki Wakimoto, Yoshihiro Yamashita, Shinkuro Sato
  • Publication number: 20140231830
    Abstract: Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal on the Ga2O3 substrate; and a nitride semiconductor layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the Ga2O3 substrate is no less than 1.0×1018/cm3.
    Type: Application
    Filed: October 12, 2012
    Publication date: August 21, 2014
    Applicants: Tamura Corporation, Koha Co., Ltd.
    Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato
  • Publication number: 20140048823
    Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga203 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer formed on the Ga203 substrate, and a nitride semiconductor layer formed on the AIN buffer layer.
    Type: Application
    Filed: April 3, 2012
    Publication date: February 20, 2014
    Applicants: KOHA CO., LTD., TAMURA CORPORATION
    Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
  • Publication number: 20140027770
    Abstract: A semiconductor laminate having small electric resistivity in the thickness direction; a process for producing the semiconductor laminate; and a semiconductor element equipped with the semiconductor laminate. include a semiconductor laminate including a Ga203 substrate; an AlGalnN buffer layer which is formed on the Ga203 substrate; a nitride semiconductor layer which is formed on the AlGalnN buffer layer and contains Si; and an Si-rich region which is formed in an area located on the AlGalnN buffer layer side in the nitride semiconductor layer and has an Si concentration of 5×1018/cm3 or more.
    Type: Application
    Filed: April 3, 2012
    Publication date: January 30, 2014
    Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato