Patents by Inventor Shinn-Sheng Yu

Shinn-Sheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11086227
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20210240087
    Abstract: A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.
    Type: Application
    Filed: January 8, 2021
    Publication date: August 5, 2021
    Inventor: Shinn-Sheng YU
  • Patent number: 11073755
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Publication number: 20210208505
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Patent number: 10976655
    Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20210096475
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Kenji YAMAZOE, Minfeng CHEN, Shuo-Yen CHOU, Chin-Hsiang LIN
  • Patent number: 10955746
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Patent number: 10867112
    Abstract: A method of making a mask includes computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the transmission cross coefficient matrix into an ideal transmission cross coefficient (TCC) kernel set for a corresponding ideal optical system and at least one perturbation kernel set with coefficients corresponding to optical defects in the optical system, calibrating a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns, and providing the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the mask using the synthesized mask layout.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Ru-Gun Liu, Shinn-Sheng Yu
  • Patent number: 10866525
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Kenji Yamazoe, Minfeng Chen, Shuo-Yen Chou, Chin-Hsiang Lin
  • Publication number: 20200379335
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 10831094
    Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200319545
    Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200310250
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10747097
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 10691014
    Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10684552
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200057375
    Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 20, 2020
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Chin-Hsiang LIN
  • Publication number: 20200050100
    Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200041915
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Kenji YAMAZOE, Minfeng CHEN, Shuo-Yen CHOU, Chin-Hsiang LIN
  • Publication number: 20200004135
    Abstract: A method of making a mask includes computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the transmission cross coefficient matrix into an ideal transmission cross coefficient (TCC) kernel set for a corresponding ideal optical system and at least one perturbation kernel set with coefficients corresponding to optical defects in the optical system, calibrating a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns, and providing the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the mask using the synthesized mask layout.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Hsu-Ting HUANG, Ru-Gun LIU, Shinn-Sheng YU