Abstract: There is provided an image sensor including a first substrate including a plurality of pixels and a plurality of vertical signal lines and a plurality of first wiring layers and a second substrate including a plurality of second wiring layers. The first and second substrates are secured together between the pluralities of first and second wiring layers. First pads are provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers and second pads are provided between another of the plurality of first wiring layers and another of the plurality of second wiring layers. First vias and second vias connect the first pads and the one of the plurality of first wiring layers and the one of the plurality of second wiring layers together.

Abstract: There is provided an image sensor including a first substrate including a plurality of pixels and a plurality of vertical signal lines and a plurality of first wiring layers and a second substrate including a plurality of second wiring layers. The first and second substrates are secured together between the pluralities of first and second wiring layers. First pads are provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers and second pads are provided between another of the plurality of first wiring layers and another of the plurality of second wiring layers. First vias and second vias connect the first pads and the one of the plurality of first wiring layers and the one of the plurality of second wiring layers together.

Abstract: There is provided an image sensor including a first substrate including a plurality of pixels and a plurality of vertical signal lines and a plurality of first wiring layers and a second substrate including a plurality of second wiring layers. The first and second substrates are secured together between the pluralities of first and second wiring layers. First pads are provided between one of the plurality of first wiring layers and one of the plurality of second wiring layers and second pads are provided between another of the plurality of first wiring layers and another of the plurality of second wiring layers. First vias and second vias connect the first pads and the one of the plurality of first wiring layers and the one of the plurality of second wiring layers together.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: Provided is a semiconductor memory device including: first and second SRAM cells; a first hit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.

Abstract: A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.

Abstract: A semiconductor memory device includes: a first word line and a second word line; a plurality of first SRAM cells; a plurality of second SRAM cells; and a mediating cell. Each first SRAM cell includes the first word line and the second word line and is connected to the first word line. Each second SRAM cell includes the first word line and the second word line and is connected to the second word line. The mediating cell is arranged between and adjacent to one first SRAM cell and one second SRAM cell and is connected to the first word line and the second word line. In the mediating cell and the plurality of first SRAM cells, cells adjacent to each other share a contact for the first word line. In the mediating cell and the plurality of second SRAM cells, cells adjacent to each other share a contact for the second word line.

Abstract: Provided is a semiconductor memory device including: first and second SRAM cells; a first hit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.

Abstract: Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.

Abstract: A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor a

Abstract: A semiconductor memory device includes: a first word line and a second word line; a plurality of first SRAM cells; a plurality of second SRAM cells; and a mediating cell. Each first SRAM cell includes the first word line and the second word line and is connected to the first word line. Each second SRAM cell includes the first word line and the second word line and is connected to the second word line. The mediating cell is arranged between and adjacent to one first SRAM cell and one second SRAM cell and is connected to the first word line and the second word line. In the mediating cell and the plurality of first SRAM cells, cells adjacent to each other share a contact for the first word line. In the mediating cell and the plurality of second SRAM cells, cells adjacent to each other share a contact for the second word line.

Abstract: Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.

Abstract: A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor provided between the output terminal of the first inverter and one line of a bit line pair, a transmission transistor provided between the output terminal of the second inverter and the other line of the bit line pair; and an isolation transistor for isolating the drive transistor and the transmission transistor. The transmission transistor, the transmission transistor, the drive transistor, and the isolation transistor are formed in a continuous active region and the isolation transistor is provided between the drive transistor and the transmission transistor.

Abstract: A semiconductor device includes a latch circuit which includes a first node for keeping a first potential corresponding to a data, and a second node for keeping a second potential corresponding to the same data, a diffusion layer continuously formed between the first node and the second node, and a transistor provided on the diffusion layer to isolate the first node from the second node.

Abstract: A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor a

Abstract: A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well.