Abstract: A pulse generating circuit that has a reset pulse generation circuit configured to output a reset pulse when an input signal changes from a first state to a second state and a set pulse generation circuit configured to output a set pulse when the input signal changes from the second state to the first state is provided. This reset/set pulse generation circuits each comprise a CMOS inverter and a delay unit. The delay unit includes a capacitor chargeable/dischargeable in response to an output signal of the CMOS inverter to output a delayed output signal. In the reset pulse generator circuit, its capacitor is connected between the CMOS inverter's output end and the power supply line. The set pulse generator circuit's capacitor is coupled between the CMOS inverter's output end and the ground line. The inverter circuit sets the output end at the power supply line before the state change of the input signal and sets this output end at the ground potential after the state change of the input signal.

Abstract: A pulse generating circuit that has a reset pulse generation circuit configured to output a reset pulse when an input signal changes from a first state to a second state and a set pulse generation circuit configured to output a set pulse when the input signal changes from the second state to the first state is provided. This reset/set pulse generation circuits each comprise a CMOS inverter and a delay unit. The delay unit includes a capacitor chargeable/dischargeable in response to an output signal of the CMOS inverter to output a delayed output signal. In the reset pulse generator circuit, its capacitor is connected between the CMOS inverter's output end and the power supply line. The set pulse generator circuit's capacitor is coupled between the CMOS inverter's output end and the ground line. The inverter circuit sets the output end at the power supply line before the state change of the input signal and sets this output end at the ground potential after the state change of the input signal.