Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: A system of making a semiconductor device by forming bumps on pads of a test piece which is a semiconductor wafer or chip is disclosed. The system includes a mask substrate having holding holes; a supply portion for supplying a bump material including liquid, which contains a plurality of individual bump materials, to a target face of the mask substrate, so as to make the bump materials be fastened to the holding holes; a compressing plate, provided at the side of the other face of the mask substrate, which can optionally be made to contact with the other face; and a cleaning station for supplying a cleaning liquid or gas to the target face of the mask substrate. After the bump materials are fastened to the holding holes and the target face is cleaned, the bump materials are pressed, together with the mask substrate, onto the pads of the test piece.

Abstract: A method of making a semiconductor device by forming bumps on pads of a test piece. The method includes a fastening process of pouring a bump material including a liquid and a plurality of individual pump materials toward a target face of a mask substrate, the mask substrate having a plurality of holding holes, and making bump materials to become fastened to the holding holes; a removing process of removing the individual bump materials remaining on the target face from the target face; and a compression process of compressing the pads of the test piece from the side of the target face of the mask substrate toward the mask substrate so as to bond the individual bump materials onto the pads. By this method, micro bump materials can be accurately attached onto pads on a silicon wafer, or the like, and the size of the mask substrate can be easily increased.

Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: Filters that have transmission wavelength characteristics that change in stages are provided. An object being inspected is specified based on spectrum characteristics that are created from image data of images that have passed through the filters and been picked up by a CCD camera. The image data as well as the spectrum characteristic data are recorded as a database on a hard disk. Then, a comparison is made between this database and the data of the object being inspected.

Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: An analytical simulator and analytical simulation method and program for determining a defective portion in a device in a short time without requiring a high level of experience and skill. The simulator has a design section for designing the device based on predetermined design data including design specification data; a test result tool for receiving results of a test on the device as an object to be analyzed, where the device is designed by the design section and is produced based on the design; and an analysis section for comparing each test result with an expected output value of the object to be analyzed, where the expected output value is calculated by the design section, and for determining a range including a defective portion in the object to be analyzed, based on results of the comparison.

Abstract: A bump forming method for forming bumps on pads of a test piece which is a semiconductor wafer or chip includes a fastening process of pouring a bump material including liquid toward a target face of a mask substrate in which a plurality of holding holes are provided, and making bump materials, included in the bump material including liquid, be fastened to the holding holes; a removing process of removing bump materials remaining on the target face of the mask substrate; and a compression process of compressing the pads of the test piece from the side of the target face of the mask substrate toward the mask substrate so as to bond the bump materials onto the pads. Micro bump materials can be accurately attached onto pads on a silicon wafer, or the like, and the size of the mask substrate can be easily increased.

Abstract: In a method for manufacturing a semiconductor device according to the present invention, a back surface on a silicon wafer is ground and, after that, mirror-finished. A breakable layer on a back surface is removed. A silicon wafer is formed in the silicon wafer has a back surface in which a crystalline layer which is disposed innermore than the breakable layer is exposed. Bumps are formed on predetermined positions on a surface on the silicon wafer. By doing this, it is possible to provide a semiconductor device and a method for manufacturing therefore in which it is possible to prevent a crack from being formed on the semiconductor base board caused by a stress in a process for forming the bumps. As a result, it is possible to improve the production yield in the process for forming the bumps. Also, it is possible to realize more integration in the semiconductor device by a lower production cost.

Abstract: A production process for a semiconductor apparatus is provided in which there is no danger of particle generation, and consequently no danger of associated problems resulting from the presence of particles, such as shorting, and which as a result, is capable of producing improved product yields, good product quality stability and improved product reliability. A resist 13b is formed on those regions of a N-type silicon substrate 1 on which wiring is not to be formed, a conductive layer 15 is formed across the entire surface of the N-type silicon substrate 1 including the resist 13b, and the conductive layer 15 is then polished by mechanical polishing, as this result, the surface of the resist 13b is exposed.

Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: In a method for manufacturing a semiconductor device according to the present invention, a back surface on a silicon wafer is ground and, after that, mirror-finished. A breakable layer on a back surface is removed. A silicon wafer is formed in the silicon wafer has a back surface in which a crystalline layer which is disposed innermore than the breakable layer is exposed. Bumps are formed on predetermined positions on a surface on the silicon wafer. By doing this, it is possible to provide a semiconductor device and a method for manufacturing therefore in which it is possible to prevent a crack from being formed on the semiconductor base board caused by a stress in a process for forming the bumps. As a result, it is possible to improve the production yield in the process for forming the bumps. Also, it is possible to realize more integration in the semiconductor device by a lower production cost.

Abstract: A surface of a silicon wafer having bump electrodes is divided in a matrix manner by scribe lines (2 and 3). The divided areas are silicon chips (4). A plurality of bumps 5 are formed on predetermined positions on the silicon chips (4). The bumps (5) are electrically conductive wear-resistant members so as to withstand repeated use. By doing this, it is possible to provide a semiconductor device which can realize a mounting operation for a semiconductor substrate of small size with high density at low cost and to measure electrical characteristics for semiconductor wafers and semiconductor chips efficiently in a manufacturing process or after a mounting operation.

Abstract: A system for forming bumps on pads which are provided on a target at low cost and with high productivity. The target is a semiconductor wafer or a semiconductor chip. The system has an attracting and compressing device for attracting bump materials for bumps, and compressing and bonding the bump materials onto the pads. The attracting and compressing device may have an attracting and compressing plate in which hollow portions for attracting and holding the bump materials are formed, the hollow portions being one of holes, concave portions, and grooves. The attracting and compressing plate can collectively attract the bump materials to be compressed onto a predetermined area which corresponds to one of a wafer, a chip, and a block. The attracting and compressing device may have a finishing plate which has a flat surface for pressing and bonding the bump materials, and an ultrasonic wave generating device.

Abstract: An analytical simulator and analytical simulation method and program for determining a defective portion in a device in a short time without requiring a high level of experience and skill. The simulator has a design section for designing the device based on predetermined design data including design specification data; a test result tool for receiving results of a test on the device as an object to be analyzed, where the device is designed by the design section and is produced based on the design; and an analysis section for comparing each test result with an expected output value of the object to be analyzed, where the expected output value is calculated by the design section, and for determining a range including a defective portion in the object to be analyzed, based on results of the comparison.