Abstract: A data transmission circuit analyzes video data and a pixel clock input from a video/audio signal processor, and determines whether the signals are valid or not. If a signal is invalid, the data transmission circuit generates and outputs a TMDS signal based on dummy video data and a dummy pixel clock internally generated as pseudo signals. Accordingly, a state in which an invalid signal is being output can be prevented, and the time required to output video can be reduced because an additional device authentication is not performed.

Abstract: An audio/video transmission apparatus includes a hot plug detecting section for detecting a hot plug signal output from a reception apparatus connected thereto via an High Definition Multimedia Interface (HDMI), an EDID reading/determining section for determining Extended Display Identification Data (EDID) information of the reception apparatus, a type determining section for determining a type of the reception apparatus based on a result of the determination of the EDID information, a TMDS switching section for designating an output scheme corresponding to the type of the reception apparatus of a plurality of Transition Minimized Differential Signaling (TMDS) signal output schemes; and a TMDS output section for outputting a TMDS signal in accordance with the designated output scheme.

Abstract: Process steps from the step of judging whether or not data transfer at a target has been completed to the step of transferring status information to a host are automated. When an error is generated, the generation of the error is notified to an external control unit and the external control unit which has received the notification performs proper error processing.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU contained LSI includes a CPUa, common address/data buses 111 and 112 connected to the CPUa, CPUb address/data buses 211 and 212 connected to a CPUb, and a bus adjusting circuit 105 disposed between the common address/data buses and the CPUb address/data buses to exclusively control accesses from the CPUa and the CPUb to a device connected to the common address/data buses and connect the CPUb adress/data buses to the common address/data buses only when the CPUb is permitted to access the device connected to the common address/data buses.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI.

Abstract: A judgment is made as to whether an ignition key is inserted into a key cylinder, and when the ignition key is inserted into the key cylinder, a keyless entry operation is forbidden. Here, a judgment is made as to whether a door on a driver's seat side is slammed shut by a driver, and when the door on the driver's seat side is slammed shut, forbiddance of locking/unlocking control is canceled according to a command signal transmitted from a transmitter.