Abstract: A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads 11 as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes 12 for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines 13 for connecting the plurality of pads 11 to the plurality of contact holes 12 correspondingly.

Abstract: A mark forming apparatus including a guide needle for forming a mark, a positioning mechanism, a solution supply device, and a heating unit is disclosed. The positioning mechanism is used for positioning the guide needle above a fault location of a semiconductor device. The solution supply device supplies a solution containing a coloring agent and a volatile solvent to the fault location until it touches a tip of the guide needle. The heating unit evaporates the volatile solvent to form a mark consisting of the coloring agent surrounding the fault location.

Abstract: A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads 11 as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes 12 for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines 13 for connecting the plurality of pads 11 to the plurality of contact holes 12 correspondingly.

Abstract: A method for fabricating a semiconductor device in which a wiring having a thickness with a high uniformity can be formed in the process of wiring formation using a dual damascene technology. In the method, an insulating film being patterned is formed on a semiconductor wafer, followed by forming a Cu film on both a wiring formation area which the insulating film is not formed and said insulating film. Then, the Cu film is mechanically polished until a step caused by a wiring layout is disappeared. After that, the Cu film on the insulating film is polished using chemical and mechanical polishing procedures to form a wiring made of the Cu film in the wiring formation area.

Abstract: A mark forming apparatus including a guide needle for forming a mark, a positioning mechanism, a solution supply device, and a heating unit is disclosed. The positioning mechanism is used for positioning the guide needle above a fault location of a semiconductor device. The solution supply device supplies a solution containing a coloring agent and a volatile solvent to the fault location until it touches a tip of the guide needle. The heating unit evaporates the volatile solvent to form a mark consisting of the coloring agent surrounding the fault location.

Abstract: A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m.

Abstract: A semiconductor memory device has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate.