Abstract: When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.

Abstract: A level shift 9, IGBT1, 2 and a AND element 10 are provided. An output DOUT is controlled to four states Hi/Lo/HiZ/artificial Hi by controlling input signals IN1, IN2, IN3, PULSE_IN. An element is protected from output short circuiting by transferring an output after a fixed time period to an artificial Hi. Furthermore NMOS are connected in parallel between two inverter circuits and the two stage of the inverter circuit is connected to the gate of NMOS. A delay circuit connecting the output of the initial state of the inverter circuit to a drain and the source of the NMOS to GND is connected to PULSE_IN of the level shift 9. Thus it is possible to almost completely eliminate temperature dependency of the delay time.

Abstract: In a method of manufacturing a semiconductor device having a first wiring extending in a first direction and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

Abstract: In a method of manufacturing a semiconductor device comprising: having a first wiring extending in a first direction; and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

Abstract: A second barrel shifter whose shift amount is equally controlled as that of a first barrel shifter for shifting input data by an optional bit is employed as a mask data generating circuit in a bit field operational arithmetic unit. Areas with transistor trains of the first and second barrel shifters are formed in parallel to an area having the same width as that of a 1-bit storage cell of a register file and shift amount control lines in both barrel shifters are set for common use so as to reduce the area occupied by a chip. In order to increase the processing speed of extracting an optional area of data, the bit field operational arithmetic unit is provided with a circuit for subjecting all bits to signal expansion in No. 0 bit data in parallel to the shift of input data effected by the first barrel shifter. Moreover, barrel shift circuits include left and right shift circuits as n shift circuits for shifting 2.sup.i -bit (i=0, 1, 2, . . . , n-1) data, with n as a positive integer.

Abstract: In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction.

Abstract: In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction.